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21 Open 13 Closed
21 Open 13 Closed
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Issues list

Feature Request: add support for running VHDL/Verilog code alongside/within RustHDL
#42 opened May 10, 2024 by parker-research
Support for Sipeed Tang Nano 9K FPGA Development Board Gowin GW1NR-9 RISC-V HDMI (Tang Nano 9k)
#41 opened Apr 4, 2024 by Cr0a3
6
How does this project works? Any papers or docs?
#35 opened Nov 25, 2023 by myrfy001
1
Request: VHDL output
#34 opened Nov 20, 2023 by tschinz
Support for BeagleV-Fire
#33 opened Nov 3, 2023 by jimkring
1
Why rename?
#32 opened Oct 14, 2023 by alexpyattaev
Dumping BRAM Contents in Simulation
#31 opened Oct 2, 2023 by ThePerfectComputer
4
Calling Simulation::add_testbench multiple times makes the simulations interfere with each other
#30 opened Jul 23, 2023 by PoignardAzur
3
Naming a signal "output" triggers a "custom attribute panicked" error message
#29 opened Jul 22, 2023 by PoignardAzur
1
Update svg dependency
#28 opened Jul 19, 2023 by PoignardAzur
Use default on LogicState enhancement New feature or request
#26 opened Jul 1, 2023 by samitbasu
@samitbasu
rust-hdl and circt
#25 opened Jun 25, 2023 by jcdutton
2
Support match expressions enhancement New feature or request
#24 opened Jun 23, 2023 by twitzelbos
Support Sum Types
#23 opened May 11, 2023 by ThePerfectComputer
2
surface nextpnr errors during build enhancement New feature or request
#21 opened Apr 17, 2023 by kpwebb
@kpwebb
1
Document the PWM device documentation Improvements or additions to documentation
#20 opened Apr 16, 2023 by samitbasu
@samitbasu
Documentation issue documentation Improvements or additions to documentation
#19 opened Apr 16, 2023 by samitbasu
@samitbasu
What's the right way to get posedge to appear in this Verilog output? bug Something isn't working
#16 opened Apr 3, 2023 by Boscop
@samitbasu
3
Support for multidimensional packed bit array enhancement New feature or request
#12 opened Mar 15, 2023 by explocion
7
Add Fixed point the support to RustHDL. Similar to the support in FIRRTL. enhancement New feature or request
#4 opened Dec 29, 2022 by samitbasu
Request: Output FIRRTL as well as Verilog enhancement New feature or request
#3 opened Dec 26, 2022 by john-terrell
ProTip! Adding no:label will show everything without a label.