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Request: Output FIRRTL as well as Verilog #3

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john-terrell opened this issue Dec 26, 2022 · 0 comments

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john-terrell commented Dec 26, 2022 •

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This would allow RustHDL to take advantage of the FIRRTL ecosystem that Chisel uses.

Spec is here

john-terrell changed the title ~~Request: Output FRRTL as well as Verilog~~ Request: Output FIRRTL as well as Verilog

samitbasu added the enhancement label

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