Feature Request: add support for running VHDL/Verilog code alongside/within RustHDL

[parker-research]

It would be awesome if this tool was similar to Verilator, in that it allowed running existing Verilog/VHDL code.

Ideally, it would support both:

• using existing testbenches (which would be valuable for porting code into RustHDL)
• using existing RTL code, with testbenches written in RustHDL (very similar to the Verilator model, but without gross C++ hassle)

Huge fan of this project, and wish there was more of it!