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DFCxx simulation synth-sv #14: Pull request #49 synchronize by Muxianesty
August 16, 2024 22:22 1m 25s dfcxx_sim
dfcxx_sim
August 16, 2024 22:22 1m 25s
DFCxx simulation main #77: Pull request #49 synchronize by Muxianesty
August 16, 2024 22:22 1m 38s dfcxx_sim
dfcxx_sim
August 16, 2024 22:22 1m 38s
DFCxx simulation synth-sv #13: Pull request #49 synchronize by Muxianesty
August 16, 2024 20:01 1m 23s dfcxx_sim
dfcxx_sim
August 16, 2024 20:01 1m 23s
DFCxx simulation main #76: Pull request #49 synchronize by Muxianesty
August 16, 2024 20:01 1m 37s dfcxx_sim
dfcxx_sim
August 16, 2024 20:01 1m 37s
DFCxx simulation main #75: Pull request #49 synchronize by Muxianesty
August 16, 2024 17:51 1m 27s dfcxx_sim
dfcxx_sim
August 16, 2024 17:51 1m 27s
DFCxx simulation synth-sv #12: Pull request #49 synchronize by Muxianesty
August 16, 2024 17:51 1m 24s dfcxx_sim
dfcxx_sim
August 16, 2024 17:51 1m 24s
DFCxx simulation synth-sv #11: Pull request #49 opened by Muxianesty
August 16, 2024 16:01 1m 44s dfcxx_sim
dfcxx_sim
August 16, 2024 16:01 1m 44s
DFCxx simulation main #74: Pull request #49 opened by Muxianesty
August 16, 2024 16:01 1m 31s dfcxx_sim
dfcxx_sim
August 16, 2024 16:01 1m 31s
DOT output format synth-sv #10: Pull request #48 opened by Muxianesty
August 15, 2024 20:06 1m 43s dfcxx_dot_output_format
dfcxx_dot_output_format
August 15, 2024 20:06 1m 43s
DOT output format main #73: Pull request #48 opened by Muxianesty
August 15, 2024 20:06 1m 34s dfcxx_dot_output_format
dfcxx_dot_output_format
August 15, 2024 20:06 1m 34s
run-tests.sh: build project with tests main #72: Commit 0474d08 pushed by ssmolov
August 15, 2024 11:29 1m 27s master
master
August 15, 2024 11:29 1m 27s
run-tests.sh: build project with tests synth-sv #9: Commit 0474d08 pushed by ssmolov
August 15, 2024 11:29 1m 30s master
master
August 15, 2024 11:29 1m 30s
rm tool-run.sh main #71: Commit 0389005 pushed by ssmolov
August 15, 2024 11:16 2m 0s master
master
August 15, 2024 11:16 2m 0s
rm tool-run.sh synth-sv #8: Commit 0389005 pushed by ssmolov
August 15, 2024 11:16 1m 33s master
master
August 15, 2024 11:16 1m 33s
run-tests.sh: fixed main #70: Commit 6a9fe0c pushed by ssmolov
August 15, 2024 11:16 1m 39s master
master
August 15, 2024 11:16 1m 39s
run-tests.sh: fixed synth-sv #7: Commit 6a9fe0c pushed by ssmolov
August 15, 2024 11:16 1m 24s master
master
August 15, 2024 11:16 1m 24s
Merge pull request #47 from ispras/fix_dfcir_offset main #69: Commit 9439c8d pushed by ssmolov
August 15, 2024 10:53 1m 37s master
master
August 15, 2024 10:53 1m 37s
Merge pull request #47 from ispras/fix_dfcir_offset synth-sv #6: Commit 9439c8d pushed by ssmolov
August 15, 2024 10:53 1m 28s master
master
August 15, 2024 10:53 1m 28s
Fixed DFCIR OffsetOp printing main #68: Pull request #47 opened by Muxianesty
August 14, 2024 14:26 1m 31s fix_dfcir_offset
fix_dfcir_offset
August 14, 2024 14:26 1m 31s
Fixed DFCIR OffsetOp printing synth-sv #5: Pull request #47 opened by Muxianesty
August 14, 2024 14:26 1m 31s fix_dfcir_offset
fix_dfcir_offset
August 14, 2024 14:26 1m 31s
Merge pull request #46 from ispras/check_verilog_ci main #67: Commit abb1719 pushed by ssmolov
August 14, 2024 10:59 2m 6s master
master
August 14, 2024 10:59 2m 6s
Merge pull request #46 from ispras/check_verilog_ci synth-sv #4: Commit abb1719 pushed by ssmolov
August 14, 2024 10:59 2m 28s master
master
August 14, 2024 10:59 2m 28s
CI workflow for SystemVerilog syntax checking synth-sv #3: Pull request #46 synchronize by Muxianesty
August 14, 2024 10:56 2m 10s check_verilog_ci
check_verilog_ci
August 14, 2024 10:56 2m 10s
CI workflow for SystemVerilog syntax checking main #66: Pull request #46 synchronize by Muxianesty
August 14, 2024 10:56 2m 49s check_verilog_ci
check_verilog_ci
August 14, 2024 10:56 2m 49s
CI workflow for SystemVerilog syntax checking synth-sv #2: Pull request #46 synchronize by Muxianesty
August 14, 2024 08:25 3m 15s check_verilog_ci
check_verilog_ci
August 14, 2024 08:25 3m 15s