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synth-sv

CI workflow for SystemVerilog syntax checking #3

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CI workflow for SystemVerilog syntax checking

CI workflow for SystemVerilog syntax checking #3

Triggered via pull request August 14, 2024 10:56
@MuxianestyMuxianesty
synchronize #46
check_verilog_ci
Status Success
Total duration 2m 10s
Artifacts –

synth-sv.yml

on: pull_request
Matrix: synthesize-system-verilog
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