[pwrmgr, top_darjeeling] Take external SoC reset into account in FSM

[neeraj-rv]

1. Internally generated reset request passed to SoC.
2. Create a sticky assertion internally to log request.
   Sticky flag cleared only upon external reset deassertion.
3. SoC transfers this request to platform to assert external reset.
4. External SoC reset deasserts after some time.
5. Pwrmgr stays in FastPwrStateRstWait state until the external SoC
   reset deasserts.
6. Boot / reset sequence continues.
7. Also fixes the external reset signal glitch filter to use the por
   reset. This is required to make sure that the external reset state
   does not self-reset once asserted and faithfully forwards that state
   to pwrmgr.
8. Added some debug visibility signals for pwrmgr.
9. Added temporary reset loop back path in pwrmgr TB to translate
   internal reset req from OT --> ext reset from SoC to OT. Needs a
   proper fix in testbench (issue [pwrmgr, top_darjeeling] Model external reset request in block- and top-level DV #22710).

[andreaskurth]

I think this can work, but we need to check and change a few things before merging, and then create some issues to follow up on

[andreaskurth]

CHANGE AUTHORIZED: hw/ip/pwrmgr/rtl/pwrmgr.sv
CHANGE AUTHORIZED: hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv
CHANGE AUTHORIZED: hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
CHANGE AUTHORIZED: hw/top_darjeeling/data/top_darjeeling.hjson
CHANGE AUTHORIZED: hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson
CHANGE AUTHORIZED: hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy.sv
CHANGE AUTHORIZED: hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv
CHANGE AUTHORIZED: hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv
CHANGE AUTHORIZED: hw/top_darjeeling/rtl/autogen/top_darjeeling.sv
CHANGE AUTHORIZED: hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv