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[hw,topgen] regenerated regs and top
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fixed review comments

Signed-off-by: Neeraj Upasani <[email protected]>
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Neeraj Upasani committed Apr 17, 2024
1 parent a9c7ca9 commit ddc55ec
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Showing 7 changed files with 89 additions and 75 deletions.
2 changes: 1 addition & 1 deletion hw/ip/pwrmgr/data/pwrmgr.hjson.tpl
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Expand Up @@ -236,7 +236,7 @@
local: "false",
expose: "true"
},

{ name: "NumRstReqs",
desc: "Number of peripheral reset requets",
type: "int",
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18 changes: 9 additions & 9 deletions hw/ip/pwrmgr/rtl/pwrmgr.sv
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Expand Up @@ -521,9 +521,9 @@ module pwrmgr
}
);

// bit1 is ext rst Do not mask.
// bit1 is ext rst Use RAW signal
// Always want to propagate to clear Reset Wait state in fast FSM
assign ext_reset_req = slow_peri_reqs.rstreqs[NumRstReqs-1] ;
assign ext_reset_req = slow_peri_reqs.rstreqs[NumRstReqs-1];

for (genvar i = 0; i < NumWkups; i++) begin : gen_wakeup_status
assign hw2reg.wake_status[i].de = 1'b1;
Expand Down Expand Up @@ -714,13 +714,13 @@ module pwrmgr
////////////////////////////////////////////////////
// Routing sstaus signal outputs for monitoring
////////////////////////////////////////////////////
assign boot_status_o.cpu_fetch_en = fetch_en_o;
assign boot_status_o.rom_ctrl_status = rom_ctrl_i;
assign boot_status_o.lc_done = pwr_lc_i.lc_done;
assign boot_status_o.otp_done = otp_rsp.otp_done;
assign boot_status_o.clk_status = pwr_clk_i;
assign boot_status_o.light_reset_req = internal_reset_req;
assign boot_status_o.strapSampled = strap_sampled;
assign boot_status_o.cpu_fetch_en = fetch_en_o;
assign boot_status_o.rom_ctrl_status = rom_ctrl_i;
assign boot_status_o.lc_done = pwr_lc_i.lc_done;
assign boot_status_o.otp_done = otp_rsp.otp_done;
assign boot_status_o.clk_status = pwr_clk_i;
assign boot_status_o.light_reset_req = internal_reset_req;
assign boot_status_o.strapSampled = strap_sampled;

////////////////////////////
/// Assertions
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24 changes: 14 additions & 10 deletions hw/ip/pwrmgr/rtl/pwrmgr_fsm.sv
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Expand Up @@ -11,7 +11,7 @@ module pwrmgr_fsm
import pwrmgr_pkg::*;
import pwrmgr_reg_pkg::*;
#(
parameter bit PwrFsmWait4ExtRst = 0
parameter bit PwrFsmWait4ExtRst = 0
) (
input clk_i,
input rst_ni,
Expand Down Expand Up @@ -112,7 +112,6 @@ module pwrmgr_fsm

// strap sample should only happen on cold boot or when the
// the system goes through a reset cycle
// [output] logic strap_sampled;

// disable processing element fetching
lc_ctrl_pkg::lc_tx_t fetch_en_q, fetch_en_d;
Expand Down Expand Up @@ -164,30 +163,35 @@ module pwrmgr_fsm
assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted :
reset_cause_q == HwReq ? all_rsts_asserted : 1'b0;


// Provide the ability to control the reset to OpenTitan RoT from an external source
// The logic below makes sure that when an internal reset request is generated,
// It is held sticky high until external SoC reset logic asserts &
// deasserts the external reset signal
// The pwrmgr fast FSM is held in FastPwrStateResetWait state until external reset deasserts
// This ensure that OT reset exit flow is synchronized with the rest of the SoC & platform
if (PwrFsmWait4ExtRst) begin : gen_wait2ext_rst

assign ext_rst_req_d = ext_reset_req_i;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
light_rst_req_q <= 0;
ext_rst_req_q <= 0;
light_rst_req_q <= 1'b0;
ext_rst_req_q <= 1'b0;
end else begin
ext_rst_req_q <= ext_rst_req_d;
if(light_rst_req_q && !ext_rst_req_d && ext_rst_req_q) begin
light_rst_req_q <= '0;
light_rst_req_q <= 1'b0;
end else if (light_rst_req_i) begin
light_rst_req_q <= 1'b1;
light_rst_req_q <= 1'b1;
end
end
end
end : gen_wait2ext_rst
else
begin : gen_no_wait2ext_rst
assign light_rst_req_q = 0;
assign ext_rst_req_q = 0;
assign ext_rst_req_d = 0;
assign light_rst_req_q = 1'b0;
assign ext_rst_req_q = 1'b0;
assign ext_rst_req_d = 1'b0;
end : gen_no_wait2ext_rst


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4 changes: 1 addition & 3 deletions hw/top_darjeeling/data/top_darjeeling.hjson
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Expand Up @@ -515,9 +515,7 @@
clock_group: "infra",
reset_connections: {
rst_ni: "lc",
rst_por_ni: "por_io_div4" //{
// name: "por_io_div4"
// },
rst_por_ni: "por_io_div4",
}
base_addrs: {
core: {hart: "0x22030000"},
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33 changes: 31 additions & 2 deletions hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv
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Expand Up @@ -1035,7 +1035,6 @@ module chip_darjeeling_asic #(
// pwrmgr interface
pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status;

// assorted ast status
ast_pkg::ast_pwst_t ast_pwst;
Expand Down Expand Up @@ -1514,6 +1513,36 @@ module chip_darjeeling_asic #(
{soc_proxy_pkg::NumFatalExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}};
assign soc_recov_alert_req =
{soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}};
// The logic below is a is a loop back path
// It listens to the internal reset request generated by the power manager
// Translates this request into an expanded pulse (modeled by the counter)
// The stretched pulse is fed back to top_darjeeling as external async soc reset request
// There is opportunity to move this logic as part of the DV test bench
// Also need the ability to asynchronously assert the external reset (pin level)
// without any internal request
logic internal_request_d, internal_request_q;
logic external_reset, count_up;
logic [3:0] count;
assign internal_request_d = pwrmgr_boot_status.light_reset_req;
always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst
if (!por_n[0]) begin
external_reset <= 1'b0;
internal_request_q <= 1'b0;
count_up <= '0;
count <= '0;
end else begin
internal_request_q <= internal_request_d;
if (!internal_request_q && internal_request_d) begin
count_up <= 1'b1;
external_reset <= 1;
end else if (count == 'd8) begin
count_up <= 0;
external_reset <= 0;
count <= '0;
end else if (count_up)
count <= count + 1;
end
end : extrst

//////////////////////
// Top-level design //
Expand Down Expand Up @@ -1565,7 +1594,7 @@ module chip_darjeeling_asic #(
.soc_intr_async_i ( '0 ),
.soc_wkup_async_i ( 1'b0 ),
// FIXME: Needs better loopback fix
.soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req),
.soc_rst_req_async_i ( external_reset ),
// FIXME_END
.soc_lsio_trigger_i ( '0 ),
.entropy_src_hw_if_req_o ( entropy_src_hw_if_req ),
Expand Down
24 changes: 0 additions & 24 deletions hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -875,7 +875,6 @@ module chip_darjeeling_cw310 #(
// pwrmgr interface
pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status;

// assorted ast status
ast_pkg::ast_pwst_t ast_pwst;
Expand Down Expand Up @@ -1363,29 +1362,6 @@ module chip_darjeeling_cw310 #(
assign srst_n = manual_in_por_button_n;


logic internal_request_d, internal_request_q;
logic external_reset, count_up;
logic [3:0] count;
assign internal_request_d = pwrmgr_boot_status.light_reset_req;
always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst
if (!por_n[0]) begin
external_reset <= 1'b0;
internal_request_q <= 1'b0;
count_up <= '0;
count <= '0;
end else begin
internal_request_q <= internal_request_d;
if (!internal_request_q && internal_request_d) begin
count_up <= 1'b1;
external_reset <= 1;
end else if (count == 'd8) begin
count_up <= 0;
external_reset <= 0;
count <= '0;
end else if (count_up)
count <= count + 1;
end
end : extrst

//////////////////////
// Top-level design //
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59 changes: 33 additions & 26 deletions util/topgen/templates/chiplevel.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -498,7 +498,9 @@ module chip_${top["name"]}_${target["name"]} #(
// pwrmgr interface
pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
% if top["name"] != "darjeeling":
pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status;
% endif

// assorted ast status
ast_pkg::ast_pwst_t ast_pwst;
Expand Down Expand Up @@ -1223,6 +1225,36 @@ module chip_${top["name"]}_${target["name"]} #(
{soc_proxy_pkg::NumFatalExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}};
assign soc_recov_alert_req =
{soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}};
// The logic below is a is a loop back path
// It listens to the internal reset request generated by the power manager
// Translates this request into an expanded pulse (modeled by the counter)
// The stretched pulse is fed back to top_darjeeling as external async soc reset request
// There is opportunity to move this logic as part of the DV test bench
// Also need the ability to asynchronously assert the external reset (pin level)
// without any internal request
logic internal_request_d, internal_request_q;
logic external_reset, count_up;
logic [3:0] count;
assign internal_request_d = pwrmgr_boot_status.light_reset_req;
always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst
if (!por_n[0]) begin
external_reset <= 1'b0;
internal_request_q <= 1'b0;
count_up <= '0;
count <= '0;
end else begin
internal_request_q <= internal_request_d;
if (!internal_request_q && internal_request_d) begin
count_up <= 1'b1;
external_reset <= 1;
end else if (count == 'd8) begin
count_up <= 0;
external_reset <= 0;
count <= '0;
end else if (count_up)
count <= count + 1;
end
end : extrst

% endif
//////////////////////
Expand Down Expand Up @@ -1297,7 +1329,7 @@ module chip_${top["name"]}_${target["name"]} #(
.soc_intr_async_i ( '0 ),
.soc_wkup_async_i ( 1'b0 ),
// FIXME: Needs better loopback fix
.soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req),
.soc_rst_req_async_i ( external_reset ),
// FIXME_END
.soc_lsio_trigger_i ( '0 ),
.entropy_src_hw_if_req_o ( entropy_src_hw_if_req ),
Expand Down Expand Up @@ -1442,31 +1474,6 @@ module chip_${top["name"]}_${target["name"]} #(
assign otp_obs_o = '0;
% endif

% if top["name"] == "darjeeling":
logic internal_request_d, internal_request_q;
logic external_reset, count_up;
logic [3:0] count;
assign internal_request_d = pwrmgr_boot_status.light_reset_req;
always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst
if (!por_n[0]) begin
external_reset <= 1'b0;
internal_request_q <= 1'b0;
count_up <= '0;
count <= '0;
end else begin
internal_request_q <= internal_request_d;
if (!internal_request_q && internal_request_d) begin
count_up <= 1'b1;
external_reset <= 1;
end else if (count == 'd8) begin
count_up <= 0;
external_reset <= 0;
count <= '0;
end else if (count_up)
count <= count + 1;
end
end : extrst
% endif

//////////////////////
// Top-level design //
Expand Down

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