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[hw,topgen] regenerated regs and top
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Signed-off-by: Neeraj Upasani <[email protected]>
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Neeraj Upasani committed Apr 17, 2024
1 parent a9c7ca9 commit 840a040
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Showing 5 changed files with 54 additions and 51 deletions.
3 changes: 3 additions & 0 deletions .bazelrc
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Expand Up @@ -139,6 +139,9 @@ build:ubsan --linkopt -fsanitize=undefined
# Enable the rust nightly toolchain
build --@rules_rust//rust/toolchain/channel=nightly

#Add Centos bin link
build --@rules_rust//:extra_rustc_toolchain_dirs=/tools/foss/llvm/13.0.1/x86_64/centos.7/bin

# Configure the rust 'clippy' linter.
build --aspects=@rules_rust//rust:defs.bzl%rust_clippy_aspect
build --output_groups=+clippy_checks
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2 changes: 1 addition & 1 deletion hw/ip/pwrmgr/data/pwrmgr.hjson.tpl
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Expand Up @@ -236,7 +236,7 @@
local: "false",
expose: "true"
},

{ name: "NumRstReqs",
desc: "Number of peripheral reset requets",
type: "int",
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26 changes: 25 additions & 1 deletion hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv
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Expand Up @@ -1515,6 +1515,30 @@ module chip_darjeeling_asic #(
assign soc_recov_alert_req =
{soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}};

logic internal_request_d, internal_request_q;
logic external_reset, count_up;
logic [3:0] count;
assign internal_request_d = pwrmgr_boot_status.light_reset_req;
always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst
if (!por_n[0]) begin
external_reset <= 1'b0;
internal_request_q <= 1'b0;
count_up <= '0;
count <= '0;
end else begin
internal_request_q <= internal_request_d;
if (!internal_request_q && internal_request_d) begin
count_up <= 1'b1;
external_reset <= 1;
end else if (count == 'd8) begin
count_up <= 0;
external_reset <= 0;
count <= '0;
end else if (count_up)
count <= count + 1;
end
end : extrst

//////////////////////
// Top-level design //
//////////////////////
Expand Down Expand Up @@ -1565,7 +1589,7 @@ module chip_darjeeling_asic #(
.soc_intr_async_i ( '0 ),
.soc_wkup_async_i ( 1'b0 ),
// FIXME: Needs better loopback fix
.soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req),
.soc_rst_req_async_i ( external_reset ),
// FIXME_END
.soc_lsio_trigger_i ( '0 ),
.entropy_src_hw_if_req_o ( entropy_src_hw_if_req ),
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23 changes: 0 additions & 23 deletions hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv
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Expand Up @@ -1363,29 +1363,6 @@ module chip_darjeeling_cw310 #(
assign srst_n = manual_in_por_button_n;


logic internal_request_d, internal_request_q;
logic external_reset, count_up;
logic [3:0] count;
assign internal_request_d = pwrmgr_boot_status.light_reset_req;
always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst
if (!por_n[0]) begin
external_reset <= 1'b0;
internal_request_q <= 1'b0;
count_up <= '0;
count <= '0;
end else begin
internal_request_q <= internal_request_d;
if (!internal_request_q && internal_request_d) begin
count_up <= 1'b1;
external_reset <= 1;
end else if (count == 'd8) begin
count_up <= 0;
external_reset <= 0;
count <= '0;
end else if (count_up)
count <= count + 1;
end
end : extrst

//////////////////////
// Top-level design //
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51 changes: 25 additions & 26 deletions util/topgen/templates/chiplevel.sv.tpl
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Expand Up @@ -1224,6 +1224,30 @@ module chip_${top["name"]}_${target["name"]} #(
assign soc_recov_alert_req =
{soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}};

logic internal_request_d, internal_request_q;
logic external_reset, count_up;
logic [3:0] count;
assign internal_request_d = pwrmgr_boot_status.light_reset_req;
always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst
if (!por_n[0]) begin
external_reset <= 1'b0;
internal_request_q <= 1'b0;
count_up <= '0;
count <= '0;
end else begin
internal_request_q <= internal_request_d;
if (!internal_request_q && internal_request_d) begin
count_up <= 1'b1;
external_reset <= 1;
end else if (count == 'd8) begin
count_up <= 0;
external_reset <= 0;
count <= '0;
end else if (count_up)
count <= count + 1;
end
end : extrst

% endif
//////////////////////
// Top-level design //
Expand Down Expand Up @@ -1297,7 +1321,7 @@ module chip_${top["name"]}_${target["name"]} #(
.soc_intr_async_i ( '0 ),
.soc_wkup_async_i ( 1'b0 ),
// FIXME: Needs better loopback fix
.soc_rst_req_async_i ( pwrmgr_boot_status.light_reset_req),
.soc_rst_req_async_i ( external_reset ),
// FIXME_END
.soc_lsio_trigger_i ( '0 ),
.entropy_src_hw_if_req_o ( entropy_src_hw_if_req ),
Expand Down Expand Up @@ -1442,31 +1466,6 @@ module chip_${top["name"]}_${target["name"]} #(
assign otp_obs_o = '0;
% endif

% if top["name"] == "darjeeling":
logic internal_request_d, internal_request_q;
logic external_reset, count_up;
logic [3:0] count;
assign internal_request_d = pwrmgr_boot_status.light_reset_req;
always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin : extrst
if (!por_n[0]) begin
external_reset <= 1'b0;
internal_request_q <= 1'b0;
count_up <= '0;
count <= '0;
end else begin
internal_request_q <= internal_request_d;
if (!internal_request_q && internal_request_d) begin
count_up <= 1'b1;
external_reset <= 1;
end else if (count == 'd8) begin
count_up <= 0;
external_reset <= 0;
count <= '0;
end else if (count_up)
count <= count + 1;
end
end : extrst
% endif

//////////////////////
// Top-level design //
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