[dv,mbx] Initial mailbox stress sequence

[alees24]

PR including some initial work on a stress test, intended to progress the mailbox DV effort at block level.

Limitations:

• Still no scoreboard; needs substantial updating.
• Checking of CSRs and interrupts is performed in the sequence (mbx_base_vseq),
  and the request and response are checked but by (i) reading from memory after the request
  has been received, and (ii) collecting and checking the response after SoC-side CSR reads.
• Does not perform any monitoring/on-the-fly checking of TL-UL read/write traffic.
• Does not attempt to catch any out-of-bounds reading/writing performed by the mailbox.
• Does not make sensible/useful decisions about the frequency of Aborts/Errors/FW-resets; it will probably be desirable to create additional stress sequences that focus upon these particular stressors and with different emphases.

Restructured sequences mimic DMA DV:

   mbx_base_vseq <- mbx_smoke_vseq
                 <- mbx_stress_vseq

Improvements over existing basic smoke test:

• Multiple request/response transactions back-to-back without intervening reset
• Multiple iterations with intervening resets
• Randomized message lengths and content.
• Randomized Abort requests from SoC side
• Randomized Error signals from Core side
• Randomized Firmware resets from Core side
• Randomized timing on all TL-UL interfaces, including a 'zero delays' stress sequence.

Note:

• Does not yet exercise Tl-UL bus/integrity errors because this explodes cip_base_scoreboard
  which is not expecting errors.
• Does not exercise Asynchronous message signaling at all.

Does trip a couple of SV assertions in the RTL which are not checking logic failures within the
RTL but rather checking that SoC/DV side is not misbehaving such as writing data when should not;
however, such events do unavoidably occur when the DV side is aborting/resetting the mailbox.
And can on the live system; should perhaps be coverage points rather than assertions?!

Closes lowRISC/opentitan-integrated#572

[alees24]

As reported by CI I'm afraid there's an oversight somewhere in my attempt to use mbx_reg_pkg within the DV environment. This was a change made to use the auto-generated offsets of the WDATA and RDATA registers within the SoC-side register address space, but it looks as though one or more FuseSoC core files needs modifying.

Also, there's an unnamed use of an isolation fork within mbx_base_vseq.sv/wait_for_core_signal. Sorry.

[hcallahan-lowrisc]

rebased

[hcallahan-lowrisc]

I pushed a couple of changes to this PR, just a rebase and then mostly minor changes to comments in some places. There is one extra commit which reduces the number of iterations/transactions to reduce the number of tests timing-out.

After spending some time reviewing the code and running some simulations, I feel confident in merging this PR as an initial stress-testing environment for the mbx at block-level. With the lack of a fleshed-out scoreboard, I think this routine does a decent job of modelling expectations of nominal message passing + random insertion of stressors (abort, error).
It also shows recovery from these conditions, with a couple of exceptions listed in the failure-buckets below (may be DV bugs, not yet fully triaged). I would plan to track these issues separately as follow-ups.

I have observed the stimulus described in the PR description in waveforms, and without block-level fcov to confirm this I think it is in a good state to be merged to progress the DV story.

## Failure Buckets

* `xmsim: *E,ASRTST (/home/harry/projects/opentitan/scratch/mbx-stress/mbx-sim-xcelium/default/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,286): Assertion ReadyAssertedWhenRead_A has failed` has 6 failures:
    * Test mbx_stress has 6 failures.
        * 1.mbx_stress.4039914985\
          Line 229, in log /home/harry/projects/opentitan/scratch/mbx-stress/mbx-sim-xcelium/1.mbx_stress/latest/run.log

                xmsim: *E,ASRTST (/home/harry/projects/opentitan/scratch/mbx-stress/mbx-sim-xcelium/default/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,286): (time 5070327633 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
                UVM_ERROR @ 5070327633 ps: (mbx_ombx.sv:286) [ASSERT FAILED] ReadyAssertedWhenRead_A
                UVM_INFO @ 5070327633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
                --- UVM Report catcher Summary ---

* `xmsim: *E,ASRTST (/home/harry/projects/opentitan/scratch/mbx-stress/mbx-sim-xcelium/default/src/lowrisc_tlul_adapter_host_*/rtl/tlul_adapter_host.sv,186): Assertion DontExceeedMaxReqs has failed` has 1 failures:
    * Test mbx_stress has 1 failures.
        * 40.mbx_stress.2302413142\
          Line 159, in log /home/harry/projects/opentitan/scratch/mbx-stress/mbx-sim-xcelium/40.mbx_stress/latest/run.log

                xmsim: *E,ASRTST (/home/harry/projects/opentitan/scratch/mbx-stress/mbx-sim-xcelium/default/src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv,186): (time 1922081005 PS) Assertion tb.dut.u_sramrwarb.u_sram_host_adapter.DontExceeedMaxReqs has failed
                UVM_FATAL @ 1922081005 ps: (tl_monitor.sv:172) [uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.monitor] Check failed pending_a_req.exists(cloned_req.a_source) == 0 (1 [0x1] vs 0 [0x0])
                UVM_INFO @ 1922081005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
                --- UVM Report catcher Summary ---