[dv,mbx] Initial mailbox stress sequence

hw/ip/mbx/dv/env/mbx_env.core

@@ -7,6 +7,7 @@ description: "MBX DV UVM environment"
 filesets:
   files_dv:
     depend:
+      - lowrisc:ip:mbx
       - lowrisc:dv:ralgen
       - lowrisc:dv:cip_lib
     files:
@@ -15,6 +16,7 @@ filesets:
       - mbx_env_cfg.sv: {is_include_file: true}
       - mbx_env_cov.sv: {is_include_file: true}
       - mbx_virtual_sequencer.sv: {is_include_file: true}
+      - mbx_seq_item.sv: {is_include_file: true}
       - mbx_scoreboard.sv: {is_include_file: true}
       - mbx_env.sv: {is_include_file: true}
       - seq_lib/mbx_tl_reg_seq.sv: {is_include_file: true}
@@ -23,6 +25,7 @@ filesets:
       - seq_lib/mbx_common_vseq.sv: {is_include_file: true}
       - seq_lib/mbx_smoke_vseq.sv: {is_include_file: true}
       - seq_lib/mbx_vseq_list.sv: {is_include_file: true}
+      - seq_lib/mbx_stress_vseq.sv: {is_include_file: true}
     file_type: systemVerilogSource
 
 generate:

hw/ip/mbx/dv/env/mbx_env_cfg.sv

@@ -5,8 +5,6 @@
 class mbx_env_cfg extends cip_base_env_cfg #(
   .RAL_T(mbx_core_reg_block)
 );
-  import dv_utils_pkg::*;
-
   string mbx_mem_ral_name = "mbx_mem_reg_block";
   string mbx_soc_ral_name = "mbx_soc_reg_block";
 

hw/ip/mbx/dv/env/mbx_env_pkg.sv

@@ -9,6 +9,7 @@ package mbx_env_pkg;
   import dv_utils_pkg::*;
   import dv_lib_pkg::*;
   import dv_base_reg_pkg::*;
+  import prim_mubi_pkg::*;
   import mbx_core_ral_pkg::*;
   import mbx_soc_ral_pkg::*;
   import mbx_mem_ral_pkg::*;
@@ -27,9 +28,16 @@ package mbx_env_pkg;
   parameter string LIST_OF_ALERTS[] = {"fatal_fault", "recov_fault"};
 
   parameter int unsigned MBX_DV_DW_SIZE_BYTES = 4;
-  parameter int unsigned MBX_DV_MAX_DW = 1023;
+  parameter int unsigned MBX_DV_MAX_DW = 1024;
+
+  // Addresses used by the mailbox DUT.
+  typedef bit [top_pkg::TL_AW-1:0] mbx_addr_t;
+  // Mailbox specification is in terms of 32-bit DWORDs.
+  typedef bit [31:0] mbx_dword_t;
+
+  `include "mbx_seq_item.sv"
+
 
-  // types
   typedef int unsigned uint_t;
   typedef enum bit {
     READ = 0,

hw/ip/mbx/dv/env/mbx_scoreboard.sv

@@ -47,9 +47,6 @@ class mbx_scoreboard extends cip_base_scoreboard #(
     // `DV_CHECK_CASE_EQ(exp_mbx_core_irq, cfg.intr_vif.pins, "Default state of interrupt pin is 0")
     forever begin
       @(cfg.intr_vif.pins);
-       //Adjusting the clk delay before running the check
-       //TLUL Write completion is taking 5-6 cyles
-       cfg.clk_rst_vif.wait_n_clks(12);
       `uvm_info(`gfn, $sformatf("Change in interrupt pin('b%b)", cfg.intr_vif.pins), UVM_LOW)
       `DV_CHECK_CASE_EQ(exp_mbx_core_irq, cfg.intr_vif.pins[MbxCoreReady], "Exp. interrupt doesn't match actual")
     end
@@ -83,7 +80,7 @@ class mbx_scoreboard extends cip_base_scoreboard #(
   task run_phase(uvm_phase phase);
     super.run_phase(phase);
     `downcast(m_mbx_soc_ral, cfg.ral_models[cfg.mbx_soc_ral_name])
-    // TODO: Renable interrupt checking once scoreboard is fully functional
+    // TODO: Re-enable interrupt checking once scoreboard is fully functional
     //fork
     //  monitor_core_interrupt();
     //  monitor_exp_core_interrupts();
@@ -109,8 +106,10 @@ class mbx_scoreboard extends cip_base_scoreboard #(
         `DV_CHECK_NE_FATAL(csr, null)
       end
       else begin
-    //    `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr))
-return;
+        // TODO: this does not yet cope with the fact that WDATA and RDATA accesses do not produce
+        // a hit in the above test, since they are not CSRs
+        // `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr))
+        return;
       end
 
       // if incoming access is a write to a valid csr, then make updates right away
@@ -187,7 +186,7 @@ return;
       end
     end
 
-// TODO: AML
+// TODO: The scoreboard needs updating and completing.
 return;
 
     // process the csr req
@@ -257,7 +256,7 @@ return;
       "outbound_read_ptr" : begin
         if(addr_phase_write) begin
           m_obmbx_ptr_q[0] = item.a_data;
-     m_obmbx_ptr = item.a_data;
+          m_obmbx_ptr = item.a_data;
         end
         if(addr_phase_read) begin
           void'(ral.outbound_read_ptr.predict(

hw/ip/mbx/dv/env/mbx_seq_item.sv

@@ -0,0 +1,86 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class mbx_seq_item extends uvm_sequence_item;
+
+  rand bit [top_pkg::TL_AW-1:0] ibmbx_base_addr;
+  rand bit [top_pkg::TL_AW-1:0] ibmbx_limit_addr;
+  rand bit [top_pkg::TL_AW-1:0] obmbx_base_addr;
+  rand bit [top_pkg::TL_AW-1:0] obmbx_limit_addr;
+
+  rand bit address_range_valid;
+  rand mubi4_t address_range_regwen;
+
+  // Sizes of Request and Response message in DWORDs
+  rand bit [10:0] request_dwords;
+  rand bit [10:0] response_dwords;
+
+  `uvm_object_utils_begin(mbx_seq_item)
+    `uvm_field_int(ibmbx_base_addr,      UVM_DEFAULT)
+    `uvm_field_int(ibmbx_limit_addr,     UVM_DEFAULT)
+    `uvm_field_int(obmbx_base_addr,      UVM_DEFAULT)
+    `uvm_field_int(obmbx_limit_addr,     UVM_DEFAULT)
+    `uvm_field_int(address_range_valid,  UVM_DEFAULT)
+    `uvm_field_enum(mubi4_t, address_range_regwen, UVM_DEFAULT)
+    `uvm_field_int(request_dwords,       UVM_DEFAULT)
+    `uvm_field_int(response_dwords,      UVM_DEFAULT)
+  `uvm_object_utils_end
+
+  //  Constructor: new
+  function new(string name = "");
+    super.new(name);
+  endfunction : new
+
+  function void set_address_range_randomization(bit enabled);
+    ibmbx_base_addr.rand_mode(enabled);
+    ibmbx_limit_addr.rand_mode(enabled);
+    obmbx_base_addr.rand_mode(enabled);
+    obmbx_limit_addr.rand_mode(enabled);
+  endfunction
+
+  constraint legal_ibmbx_addr_range_c {
+    // TODO: Should have a full 32-bit address space!
+    (ibmbx_limit_addr < 32'h4000_0000);
+
+    (ibmbx_limit_addr >= ibmbx_base_addr);
+    // Ensure that the allocated address range is large enough for all valid messages because
+    // otherwise we run the risk of making all subsequent response messages artificially small
+    // because the address range has been locked.
+    ((ibmbx_limit_addr - ibmbx_base_addr) / 4 >= MBX_DV_MAX_DW);
+  }
+
+  constraint legal_obmbx_addr_range_c {
+    // TODO: Should have a full 32-bit address space!
+    (obmbx_limit_addr < 32'h4000_0000);
+
+    (obmbx_limit_addr >= obmbx_base_addr);
+  }
+
+  constraint legal_address_range_valid_c {
+    // TODO: presently we are concerned only with generating valid hardware configurations.
+    address_range_valid == 1'b1;
+  }
+
+  constraint legal_request_dwords_c {
+    request_dwords > 0 && request_dwords < 'h400;
+  }
+
+  constraint legal_response_dwords_c {
+    // There is an additioanl constraint upon the length of the Response because the register
+    // OUTBOUND_OBJECT_SIZE is limited.
+    response_dwords > 0 && response_dwords <= MBX_DV_MAX_DW;
+  }
+
+  constraint legal_non_overlapping_region_c {
+    ibmbx_limit_addr < obmbx_base_addr || ibmbx_base_addr > obmbx_limit_addr;
+  }
+
+  constraint legal_addr_alignment_c {
+    (ibmbx_base_addr[1:0] == 0);
+    (ibmbx_limit_addr[1:0] == 0);
+    (obmbx_base_addr[1:0] == 0);
+    (obmbx_limit_addr[1:0] == 0);
+  }
+
+endclass : mbx_seq_item