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Membkdr #29841

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Membkdr

Membkdr #29841

Triggered via pull request January 17, 2024 23:01
@neeraj-rvneeraj-rv
opened #20863
Status Success
Total duration 1m 25s
Artifacts 1

pr_lint_review.yml

on: pull_request_target
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23 warnings
[verible-verilog-lint] hw/top_darjeeling/ip/ast/rtl/vcaon_pgd.sv#L34: hw/top_darjeeling/ip/ast/rtl/vcaon_pgd.sv#L34
Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_sram_ctrl_scrambled_access_vseq.sv#L20: hw/top_darjeeling/dv/env/seq_lib/chip_sw_sram_ctrl_scrambled_access_vseq.sv#L20
Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_sram_ctrl_scrambled_access_vseq.sv#L21: hw/top_darjeeling/dv/env/seq_lib/chip_sw_sram_ctrl_scrambled_access_vseq.sv#L21
Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_sleep_pin_wake_vseq.sv#L116: hw/top_darjeeling/dv/env/seq_lib/chip_sw_sleep_pin_wake_vseq.sv#L116
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv#L571: hw/top_darjeeling/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv#L571
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
[verible-verilog-lint] hw/dv/sv/mem_bkdr_util/mem_bkdr_util.sv#L656: hw/dv/sv/mem_bkdr_util/mem_bkdr_util.sv#L656
659:46: The lines can't be continued with '\', use concatenation operator with braces [Style: forbid-line-continuations] [forbid-line-continuations]
[verible-verilog-lint] hw/dv/sv/mem_bkdr_util/mem_bkdr_util.sv#L670: hw/dv/sv/mem_bkdr_util/mem_bkdr_util.sv#L670
672:47: The lines can't be continued with '\', use concatenation operator with braces [Style: forbid-line-continuations] [forbid-line-continuations]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_sensor_ctrl_status_intr_vseq.sv#L19: hw/top_darjeeling/dv/env/seq_lib/chip_sw_sensor_ctrl_status_intr_vseq.sv#L19
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_lc_ctrl_scrap_vseq.sv#L34: hw/top_darjeeling/dv/env/seq_lib/chip_sw_lc_ctrl_scrap_vseq.sv#L34
Do not use $test$plusargs to access plusargs, use $value$plusargs instead. [Style: plusarg-value-assignment] [plusarg-assignment]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_uart_rand_baudrate_vseq.sv#L14: hw/top_darjeeling/dv/env/seq_lib/chip_sw_uart_rand_baudrate_vseq.sv#L14
Explicitly define a storage type for every parameter and localparam, (NCO_WIDTH). [Style: constants] [explicit-parameter-storage-type]
[verible-verilog-lint] hw/top_darjeeling/ip/ast/rtl/vio_pgd.sv#L34: hw/top_darjeeling/ip/ast/rtl/vio_pgd.sv#L34
Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]
[verible-verilog-lint] hw/top_darjeeling/ip/ast/rtl/vcmain_pgd.sv#L34: hw/top_darjeeling/ip/ast/rtl/vcmain_pgd.sv#L34
Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_spi_passthrough_vseq.sv#L129: hw/top_darjeeling/dv/env/seq_lib/chip_sw_spi_passthrough_vseq.sv#L129
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
[verible-verilog-lint] hw/top_darjeeling/ip/ast/rtl/vcc_pgd.sv#L34: hw/top_darjeeling/ip/ast/rtl/vcc_pgd.sv#L34
Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_padctrl_attributes_vseq.sv#L307: hw/top_darjeeling/dv/env/seq_lib/chip_padctrl_attributes_vseq.sv#L307
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
[verible-verilog-lint] hw/ip/mbx/dv/env/mbx_scoreboard.sv#L54: hw/ip/mbx/dv/env/mbx_scoreboard.sv#L54
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
[verible-verilog-lint] hw/ip/mbx/dv/env/mbx_scoreboard.sv#L69: hw/ip/mbx/dv/env/mbx_scoreboard.sv#L69
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
[verible-verilog-lint] hw/ip/mbx/dv/env/mbx_scoreboard.sv#L247: hw/ip/mbx/dv/env/mbx_scoreboard.sv#L247
Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default]
[verible-verilog-lint] hw/ip/mbx/dv/env/mbx_scoreboard.sv#L323: hw/ip/mbx/dv/env/mbx_scoreboard.sv#L323
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/ip/mbx/dv/env/mbx_scoreboard.sv#L333: hw/ip/mbx/dv/env/mbx_scoreboard.sv#L333
Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default]
[verible-verilog-lint] hw/ip/mbx/dv/env/mbx_scoreboard.sv#L348: hw/ip/mbx/dv/env/mbx_scoreboard.sv#L348
Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
[verible-verilog-lint] hw/ip/lc_ctrl_v1/dv/env/seq_lib/lc_ctrl_v1_errors_vseq.sv#L859: hw/ip/lc_ctrl_v1/dv/env/seq_lib/lc_ctrl_v1_errors_vseq.sv#L859
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/top_darjeeling/dv/env/seq_lib/chip_sw_power_virus_vseq.sv#L160: hw/top_darjeeling/dv/env/seq_lib/chip_sw_power_virus_vseq.sv#L160
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]

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