Membkdr #20863
Closed
Membkdr #20863
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Michael Schaffner <[email protected]>
Rewind memory address at the start of chunk when auto-increment is not used at the memory end. Rewind FIFO address at the start of chunk when auto-increment is enabled. Update register description and theory of operation. Signed-off-by: Adrian Lees <[email protected]>
The valid range indicates the enabled memory range holds a valid configuration. Only if this register is set, the DMA will start working. The enabled memory range can further be locked Signed-off-by: Robert Schilling <[email protected]>
Includes mbx tb along with env, seq_lib and mbx_sim_cfg.hjson First pass smoke test with Mailbox data exchance Basic Self-checking enabled Pending, abort and interrup content. Signed-off-by: Kevin Virgen <[email protected]> Signed-off-by: Harry Callahan <[email protected]>
Fixes lingering references to old transfer_width encoding; in particular the source/dest address were unchecked in 4B/txn. Moves the enum encoding from the DV into the RTL pkg. Adds a few explanatory comments. Signed-off-by: Adrian Lees <[email protected]>
No functional change. Signed-off-by: Adrian Lees <[email protected]>
Ensure in post-randomization that the 'clear interrupt' addresses do not collide with the memory buffers. Retain the interrupt clear addresess for multi-chunk transfers. Extend register access in scoreboard to support the additional interrupt sources. Signed-off-by: Adrian Lees <[email protected]>
Support for 'chunk_data_size' parameter. Introduce constraints to ensure that the memory buffers do not overlap. Support for permutations of `memory_buffer_auto_increment_enable`, `fifo_auto_increment_enable` and `data_direction` in hardware-handshake mode. Signed-off-by: Adrian Lees <[email protected]>
Register index function already exists. Endian swap may be achieved with simple xor. Signed-off-by: Adrian Lees <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
This is only a SW fix since it does not impact the RTL. Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
This fixes the capture of hash_process signal across the 32-bit interfacing and into the SHA-2 engine for a certain corner case. This should fix issue lowRISC/opentitan-integrated#643 identified in DV. Signed-off-by: Ghada Dessouky <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
Explanatory comments. Extended reg_write handling. No functional change to existing tests. Change `randomize_item` naming to be consistent because it should should probably be common in a base class later. Signed-off-by: Adrian Lees <[email protected]>
Remove 'align_address' flag affecting randomization since new constraints provide this functionality where it is required to ensure a valid configuration. Signed-off-by: Adrian Lees <[email protected]>
Supports 'range_valid' configuration bit. Refines constraints relating to the DMA-enabled memory range. Signed-off-by: Adrian Lees <[email protected]>
SHA is only intended to operate on 32-bit transactions. Constrain to full 32-bit words for now, pending fix. Signed-off-by: Adrian Lees <[email protected]>
Checking of configuration validity (required by scoreboard to form of prediction of whether DMA controller shall reject it). Reporting of invalid configuration properties. Bring up of `dma_generic_stress` sequence. Signed-off-by: Adrian Lees <[email protected]>
Convert sequence item (configuration and transfer properties) to a string for diagnostic/logging purposes. Signed-off-by: Adrian Lees <[email protected]>
Introduces a run_opt to the test settings to allow verification of the SoC System bus to be waived within the DV environment. Settings default to disabling the waiver, ie. tests that select from the full set of ASIDs shall be expected to fail without this run opt. Verification of the SoC System bus is to be performed externally. Signed-off-by: Adrian Lees <[email protected]>
This moves most unused bytes from the CREATOR_SW_CFG and OWNER_SW_CFG partitions to the ROM_PATCH partition. However, in order to accommodate future changes, unused bytes are left within the CREATOR_SW_CFG and OWNER_SW_CFG partitions. This increases the size of the ROM_PATCH partition from 9200 to 9784 bytes. Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Andreas Kurth <[email protected]>
This closes lowRISC/opentitan-integrated#594. Signed-off-by: Andreas Kurth <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
Memory limit interrupts must be signaled on receipt of the write response, which may occur in two FSM states. Signed-off-by: Adrian Lees <[email protected]>
Instead of only using the next state signal of the FSM, we also take into account the current state, to compute the transition edge into the Read and Abort state, that generates the event for the IRQ primitive. Closes lowRISC/opentitan-integrated#714 Signed-off-by: Robert Schilling <[email protected]>
Signed-off-by: Ravi Sahita <[email protected]>
We do not have an MMIO mapped flash controller, so this access generated a fault. Signed-off-by: Samuel Ortiz <[email protected]>
This was sometimes failing. It seems that the "wait 500 cycles" delay that was in the code was on the edge, and got pushed over if the EDN clk_rst_if happened to stay in reset for a bit too long. Explicitly wait to be out of reset and then divide the wait blocks between the two clocks in a way that should hopefully be a bit more robust. Signed-off-by: Rupert Swarbrick <[email protected]>
…fterFenceI_A Signed-off-by: Robert Schilling <[email protected]>
Signed-off-by: Harry Callahan <[email protected]>
- Use cip ral_model_names mechanism to create a TL-agent for mbx_tl - Requires matching clk_rst_vif set in tb.sv - Initialize the mailbox memory for simulation - Create a basic interface (mbx_if.sv) for connection of mailbox signals - Mostly wraps the mbx-specific top level interfaces Signed-off-by: Harry Callahan <[email protected]>
See mbx_smoketest.c / chip_sw_mbx_smoke_vseq.sv headers for detailed description. Signed-off-by: Harry Callahan <[email protected]>
This updates Darjeeling's datasheet with what is currently on `master`. In detail, under `hw/top_darjeeling/`: - `doc/specification.md` gets renamed to `doc/datasheet.md` and overwritten with the contents of the latter currently on `master` - references to `doc/specification.md` get updated to `doc/datasheet.md` - `doc/top_darjeeling_block_diagram.sv` gets updated to the version that is currently on `master` - the logo in `doc/darjeeling.png` was just a copy of the Earlgrey logo (in `hw/top_earlgrey/doc/earlgrey.png`), so it doesn't serve to distinguish Darjeeling from Earlgrey and gets deleted. The contents of `hw/top_darjeeling/doc/design` do *not* get updated in this commit; this is left to follow-up work. Signed-off-by: Andreas Kurth <[email protected]>
The existing code would spit out a warning message (at UVM_HIGH so it's hard to find!), but the code that calls await_use() is written to assume that the register file in question is in use when the task finishes. Signed-off-by: Rupert Swarbrick <[email protected]>
This task is supposed to start an OTBN run and then finish when the run is still in progress. A recent change to this vseq altered things so that "in progress" includes "in the middle of the secure wipe at the end". Unfortunately, this change can break some vseqs. In particular, otbn_rf_base_intg_err_vseq expects to be able to corrupt the RF and have it cause an error. I think an opportune time to do so is no longer guaranteed to happen after the run completes and we're in the middle of secure wipe. Tighten the definition again, which I think will fix the problem. Signed-off-by: Rupert Swarbrick <[email protected]>
This wait wasn't quite long enough. I think an example program was sitting blocked waiting for RND, which consumed the 2000 cycles. An extra factor of 10 seems to be enough. Signed-off-by: Rupert Swarbrick <[email protected]>
Modify documentation to specify that the mailbox limit addresses are inclusive and indicate the final usable DWORD location. Update DIF address checks accordingly. Signed-off-by: Adrian Lees <[email protected]>
…heet Signed-off-by: Andreas Kurth <[email protected]>
We have disabled Generic / Firmware mode for `spi_device` in 02c15bb. In that commit, we also disabled the tests that work only in that mode. However, `spi_device_stress_all_vseq` still runs vseqs from tests that got disabled in the aforementioned commit. This commit removes those vseqs from `spi_device_stress_all_vseq`. Signed-off-by: Andreas Kurth <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
The path used to publish the reports of top-level IPs for Darjeeling is currently wrong, as can be seen in the links of the [summary page][1]: - ALERT_HANDLER: https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/alert_handler/dv/latest/report.html - CLKMGR: https://reports.opentitan.org/hw/ip/clkmgr/dv/latest/report.html - PWRMGR: https://reports.opentitan.org/hw/ip/pwrmgr/dv/latest/report.html - RSTMGR: https://reports.opentitan.org/hw/ip/rstmgr/dv/latest/report.html All links miss the `integrated/` prefix after the domain name, so the link for `alert_handler` cannot be found and the links for `clkmgr` and `rstmgr` collide with the results for Earlgrey (`pwrmgr` does not collide because it lives under `hw/top_earlgrey/ip_autogen/pwrmgr` on `master`). When printing the commands used to publish the results (invoking `dvsim` with `--verbose=debug`), we can see that the absolute path to the local source path is included in the remote path; for example: https://reports.opentitan.org/integrated//home/dev/src/hw/ip/clkmgr/dv//latest/report.html when `dvsim` is run inside an OpenTitan container (the local source path for the regression runner that publishes the results is likely different). The reason for this is that `rel_path` for the top-level IPs in `hw/top_darjeeing/dv/top_darjeeling_sim_cfgs.hjson` includes `{proj_root}`, which resolves to an absolute path. This commit fixes the problem by removing `{proj_root}` (and the trailing slash) from `rel_path` of Darjeeling's top-level IPs. [1]: https://reports.opentitan.org/integrated/hw/top_darjeeling/dv/summary/latest/report.html Signed-off-by: Andreas Kurth <[email protected]>
This timeout needs easing for the situation where we try to cause an alert (by setting the LC escalation signal) near the start of time. This will only be reported once the secure wipe is complete, but that takes a while! The previous wait (400 cycles) is not enough for the integrated layout. Signed-off-by: Rupert Swarbrick <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
The files containing the changes were copied from `keymgr` but the module name had not been changed from `keymgr` to `keymgr_dpe`, whereas the name of the enable input from lifecycle controller had been changed to contain the `dpe_` infix even though it should not. Signed-off-by: Andreas Kurth <[email protected]>
This parameter is defined in `keymgr_pkg`, not `keymgr_dpe_pkg`. Signed-off-by: Andreas Kurth <[email protected]>
`keymgr_dpe_common_vseq` has been created by copying `keymgr_common_vseq` and replacing `keymgr` with `keymgr_dpe` where appropriate. This is necessary to run `keymgr_dpe_csr_rw` and `keymgr_dpe_csr_hw_reset`, which are part of the `smoke` regression suite. Signed-off-by: Andreas Kurth <[email protected]>
This will execute `keymgr_dpe`'s smoke tests as part of CI regressions and its nightly regression suite as part of the nightlies. Signed-off-by: Andreas Kurth <[email protected]>
Updates contain:
1. completed handling of multiple subwords within a work (memory entry) for mem during
(a) randomization routines
(b) data generations routines
2. Added support for interleaved memory bit handling
3. Added support for sram scrambing before integrity
Signed-off-by: Neeraj Upasani <[email protected]>
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
No description provided.