Using NAS in an FPGA

Supported IDEs, simulators and devices

IDEs and simulators

Files generated by OpenNAS are currently compatible with VHDL versions from VHDL'93 in advance. They are also supported by Verilog 95 and Verilog 2001 versions.

OpenNAS has been tested for synthesis and bitfile generation with the following IDEs:

• Xilinx ISE 14.1.
• Xilinx Vivado (versions from 2016.1 to 2020.1) in several editions: WebPack, Systems Edition, HLS, etc.
• Intel Quartus Prime.

For simulations, OpenNAS has been simulated in:

• ISim from Xilinx ISE 14.1.
• Vivado integrated simulator (versions from 2016.1 to 2020.1).
• ModelSim (versions from PE 9.2B to PE 10.5C) from Intel Quartus Prime

Devices

OpenNAS was conceived as a technology- and manufacturer-independent design in order to allow the community to use it with its preferred FPGA-based platform. According to our possibilities, and with the aim to provide technical support to the users, the OpenNAS output files hab been synthesized and tested in the following FPGA chips:

• Xilinx Spartan 3.
• Xilinx Virtex 5.
• Xilinx Spartan 6.
• Xilinx Artix 7.
• Xilinx Kintex 7.
• Xilinx Zynq-7000 SoC.
• Xilinx Zynq UltraScale+ SoC.
• Intel Cyclone IV.
• Intel Cyclone V.
• Intel Arria 10.

However, if you have successfully tried OpenNAS in any other device that does not appear in the list, please let us know. We will add it!

Running the generated NAS model on an FPGA

For running the .tcl script to generate the .bit file automatically, please follow the next steps:

1. Open "ISE Design Suite 32/64 Bit Command Prompt" or "Vivado 20xx Tcl Shell".
2. Change the directory to the folder that contains the .tcl file.
3. Then, type: xtclsh file_name.tcl (when using ISE) or source file_name.tcl (when using Vivado).
4. Wait until the message "Programming File was generated successfully" appears.

Then, follow this tutorial to load the NAS bitfile in an FPGA:

Running NAS in the AER Node board.