Step 4: NAS neuromorphic output interface
To finish the NAS configuration, the output interface can be selected in step 4. This selection is conditioned by your project application, since depending on that you will need to interface the NAS to a computer, to another FPGA or to a neuromorphic platform as SpiNNaker.
By default, the AER interface is selected. This is because the AER protocol is supported by most of the neuromorphic software and hardware platforms. Therefore, if the user needs to visualize the NAS' output in real-time or sends the NAS' output events to another hardware platform, this option must be selected. It has some parameters:
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Spikes to monitor: this parameter cannot be changed. Its value is calculated as the product of the number of frequency channels, the output events polarity (POSITIVE = NEGATIVE = 1; MERGED = 2) and if the NAS is MONO (1) or STEREO (2). In this case, 64 frequency channels * STEREO * POLARITY = 64 * 2 * 2 = 256.
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Spikes FIFO Bits: size of the FIFO in which out NAS spikes will be written.
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AER FIFO Bits: size of the FIFO in which out AER events will be written.
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Total Bits: this parameter cannot be changed. Its value depends on the values specified in the above parameters.
To visualize the NAS' output in real-time, or to perform some recordings, it will need to select as NAS output the AER interface along with a specific software tool which allows us to get the output AER events from the NAS and plot them in a specific format. The most popular software tool for that purpose is jAER. After recordings, the user can use the NAVIS tool to analyze the samples files obtained from the NAS output, due to that software has been specifically developed for this purpose.
OpenNAS offers the user the possibility to connect the NAS with the SpiNNaker board (either SpiNN-3 or SpiNN-5) and to send the NAS' output spikes to an SNN deployed on SpiNNaker in real-time. Version 1 allows only the communication from the NAS to the SpiNNaker.
For doing this, we followed this tutorial about how to interface CAVIAR AER boards with SpiNNaker, and also this tutorial in which explains how to interface AER devices with SpiNNaker.
In the second tutorial, a Verilog file named "spinn_aer_if.v" is provided. That code has been adapted to make it compatible with the NAS design and to ensure the correct operation with the SpiNNaker board. In addition, the ExternalCochleaDevice class from the pyNN library has been modified to support the NAS. Follow the steps indicated here to download and configure the environment to work with the NAS and SpiNNaker in real time.
Version 2 of the AER-SpiNNaker interface allows a bidirectional communication between NAS and SpiNNaker. Then, applications that require to close the loop between the AER device and the SpiNNaker board must use this version.
In this case, the SpiNNaker spio library was used and adapted to be able to run along with the NAS. Details about the original implementation can be found in the AppNote 8 "Interfacing AER devices to SpiNNaker using an FPGA".
An example could be a robot which follows a sound source. The input audio is processing by the NAS. The NAS output will be sent to the SpiNNaker board to be processed by an SNN. Finally, the classification output can be sent back to the FPGA where the NAS was deployed, controlling the robot's motors.
The NAS output is connected at the same time to the AER interface and to the SpiNNaker interface. This way, the user can visualize what is the NAS output which is being sent to the SpiNNaker in real-time. Otherwise, either or to visualize the NAS output using jAER or to send the NAS output to SpiNNaker.
C-element is required for this option. This means that in the output both ACK (from AER monitor and from SpiNNaker interface) are required. Then, the NAS output event rate could decrease.
AER events from the NAS output are directly sent through the USB connector. This option is not available when AERNode board has been selected as NAS chip.
If the AER Interface option has been selected, a specific purpose hardware is needed to monitor the AER events and send them to a computer. However, if your FPGA-based board has a USB connector, this output interface could work. Note that more hardware configuration is needed to use this option.
