csr: fix interrupt priority (#2480)

OpenXiangShan · Nov 15, 2023 · 43171c7 · 43171c7
1 parent 4e47182
commit 43171c7
Showing 1 changed file with 6 additions and 6 deletions.
diff --git a/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala b/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
@@ -203,17 +203,17 @@ trait HasCSRConst {
   def ModeS     = 0x1.U
   def ModeU     = 0x0.U
 
-  def IRQ_UEIP  = 0
-  def IRQ_SEIP  = 1
-  def IRQ_MEIP  = 3
+  def IRQ_USIP  = 0
+  def IRQ_SSIP  = 1
+  def IRQ_MSIP  = 3
 
   def IRQ_UTIP  = 4
   def IRQ_STIP  = 5
   def IRQ_MTIP  = 7
 
-  def IRQ_USIP  = 8
-  def IRQ_SSIP  = 9
-  def IRQ_MSIP  = 11
+  def IRQ_UEIP  = 8
+  def IRQ_SEIP  = 9
+  def IRQ_MEIP  = 11
 
   def IRQ_DEBUG = 12