Skip to content
@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

Pinned Loading

  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 5k 669

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    TeX 356 136

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 68 34

  4. fudian fudian Public

    Open source high performance IEEE-754 floating unit

    Scala 61 24

  5. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 122 68

  6. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 47 48

Repositories

Showing 10 of 69 repositories
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan’s past year of commit activity
    Scala 4,961 669 59 51 Updated Dec 13, 2024
  • Utility Public
    OpenXiangShan/Utility’s past year of commit activity
    Scala 7 16 0 7 Updated Dec 13, 2024
  • NEMU Public
    OpenXiangShan/NEMU’s past year of commit activity
    C 243 94 31 18 Updated Dec 13, 2024
  • GEM5 Public
    OpenXiangShan/GEM5’s past year of commit activity
    C++ 68 BSD-3-Clause 28 12 11 Updated Dec 13, 2024
  • Deterload Public

    Xiangshan deterministic workloads generator

    OpenXiangShan/Deterload’s past year of commit activity
    Nix 10 MulanPSL-2.0 3 2 0 Updated Dec 13, 2024
  • ready-to-run Public
    OpenXiangShan/ready-to-run’s past year of commit activity
    Shell 4 8 3 0 Updated Dec 13, 2024
  • YunSuan Public

    This repo includes XiangShan's function units

    OpenXiangShan/YunSuan’s past year of commit activity
    Scala 15 MulanPSL-2.0 11 0 0 Updated Dec 13, 2024
  • rocket-chip Public Forked from chipsalliance/rocket-chip

    Rocket Chip Generator

    OpenXiangShan/rocket-chip’s past year of commit activity
    Scala 4 1,147 0 2 Updated Dec 13, 2024
  • riscv-isa-sim Public Forked from riscv-software-src/riscv-isa-sim

    Spike, a RISC-V ISA Simulator

    OpenXiangShan/riscv-isa-sim’s past year of commit activity
    C 6 883 0 1 Updated Dec 13, 2024
  • CoupledL2 Public

    Open-source non-blocking L2 cache

    OpenXiangShan/CoupledL2’s past year of commit activity
    Scala 33 20 0 3 Updated Dec 13, 2024
View all repositories

Top languages

Loading…

Most used topics

Loading…