Bump CPL2 to master@Nov14 with timing fixes (#2476) · OpenXiangShan/XiangShan@4e47182

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Bump CPL2 to master@Nov14 with timing fixes (#2476)

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Ivyfeather authored Nov 14, 2023

1 parent 2072875 commit 4e47182

+1 −3		src/main/scala/coupledL2/Common.scala
+3 −0		src/main/scala/coupledL2/DataStorage.scala
+6 −5		src/main/scala/coupledL2/GrantBuffer.scala
+7 −80		src/main/scala/coupledL2/MSHR.scala
+9 −19		src/main/scala/coupledL2/MSHRBuffer.scala
+0 −3		src/main/scala/coupledL2/MSHRCtl.scala
+3 −29		src/main/scala/coupledL2/SinkB.scala
+0 −1		src/main/scala/coupledL2/Slice.scala