UVM_Learning_v1.0

This release features a complete UVM testbench for verifying an 8-bit counter design, developed as part of the Introduction to UVM course from Verification Academy. The testbench includes key UVM components such as driver, monitor, sequencer, predictor, and scoreboard, along with dedicated test sequences for reset, increment, load, and random operations. The environment integrates all components, with TLM FIFOs enabling predictor-scoreboard communication and parallel sequence execution. Verified using Verilator, this project serves as a hands-on example of UVM-based verification. Feedback and suggestions for improvement are welcome.