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1. caravel_BrqRV_EB1 caravel_BrqRV_EB1 Public

   Forked from efabless/caravel_user_project

   https://caravel-user-project.readthedocs.io

   Verilog 1

2. GPIO_UVM_Framwork GPIO_UVM_Framwork Public

   This repository provides a UVM framework for verifying GPIO peripherals with an AXI4-Lite interface. It offers a modular, scalable testbench to ensure functional correctness and robustness, serving…

   SystemVerilog 2

3. UVM_Learning UVM_Learning Public

   This repository is a personal learning space where I explore and practice the Universal Verification Methodology (UVM). It's designed to document my progress, experiments, and understanding of UVM …

   SystemVerilog

4. merldsu/RISCV_Pipeline_Core merldsu/RISCV_Pipeline_Core Public

   This repository contains the design files of RISC-V Pipeline Core

   Verilog 34 9

5. merldsu/RISCV_Single_Cycle_Core merldsu/RISCV_Single_Cycle_Core Public

   This repository contains the design files of RISC-V Single Cycle Core

   Verilog 30 9