UVM_Learning_v2.0

This release marks the completion of a comprehensive UVM-based testbench for verifying the functionality of an 8-bit counter design. The testbench follows Universal Verification Methodology (UVM) principles, ensuring a modular, reusable, and scalable approach to functional verification. The most significant update in this release is the introduction of the UVM Agent, which now encapsulates the driver, monitor, and sequencer, simplifying the testbench structure and enhancing modularity. The agent’s analysis port is connected to the predictor and scoreboard through TLM FIFOs, facilitating seamless communication and data flow between the components. Test sequences, including operations like reset, increment, load, and random scenarios, are now managed externally, providing greater flexibility in testing different scenarios. The use of UVM Config DB enables dynamic configuration, streamlining communication and setup across components. This release ensures robust coverage of the counter’s functionality, including all primary operations, and provides a foundation for future extensions and reusable testbenches. The modular design makes it easy to adapt and integrate into other verification projects, reinforcing the power of UVM in structuring verification tasks. Feel free to explore the code and contribute your feedback for further improvements.

UVM_Learning_v1.0

This release features a complete UVM testbench for verifying an 8-bit counter design, developed as part of the Introduction to UVM course from Verification Academy. The testbench includes key UVM components such as driver, monitor, sequencer, predictor, and scoreboard, along with dedicated test sequences for reset, increment, load, and random operations. The environment integrates all components, with TLM FIFOs enabling predictor-scoreboard communication and parallel sequence execution. Verified using Verilator, this project serves as a hands-on example of UVM-based verification. Feedback and suggestions for improvement are welcome.