Fix some filepathes

Signed-off-by: Jonas K. <[email protected]>

.github/workflows/fabric_gen.yml

@@ -31,14 +31,14 @@ jobs:
             - name: Lint with flake8
               run: |
                   # stop the build if there are Python syntax errors or undefined names
-                  flake8 fabric_generator/ --count --select=E9,F63,F7,F82 --show-source --statistics
+                  flake8 FABulous/fabric_generator/ --count --select=E9,F63,F7,F82 --show-source --statistics
                   # exit-zero treats all errors as warnings. The GitHub editor is 127 chars wide
-                  flake8 fabric_generator --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics
+                  flake8 FABulous/fabric_generator --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics
             - name: Run fabric generator flow
               run: |
                   export FAB_ROOT=.
-                  python3.9 FABulous.py -c demo
-                  python3.9 FABulous.py demo --script ./demo/FABulous.tcl
+                  python3.9 FABulous/FABulous.py -c demo
+                  python3.9 FABulous/FABulous.py demo --script ./demo/FABulous.tcl
 
             - name: Run simulation smoketest
               run: |

FABulous/fabric_files/FABulous_project_template_verilog/Test/README.md

@@ -1,4 +1,4 @@
-This assumes the default instructions were followed to build a 8x14 fabric in `../fabric_generator`.
+This assumes the default instructions were followed to build a 8x14 fabric in `../../fabric_generator`.
 
 Latest Yosys and `nextpnr-generic` from upstream (_not_ the old FABulous nextpnr fork) are used
 to build the test design.

FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh

@@ -1,6 +1,6 @@
 #!/usr/bin/env bash
-SYNTH_TCL=../../fabric_cad/synth/synth_fabulous.tcl
-BIT_GEN=../../fabric_cad/bit_gen.py
+SYNTH_TCL=../../FABulous/fabric_cad/synth/synth_fabulous.tcl
+BIT_GEN=../../FABulous/fabric_cad/bit_gen.py
 
 DESIGN=counter
 

FABulous/fabric_files/FABulous_project_template_verilog/Test/run_emulation_sim.sh

@@ -1,17 +1,14 @@
 #!/usr/bin/env bash
 set -ex
 DESIGN=counter
-BITSTREAM=test_design/${DESIGN}.bin
-VERILOG=../../fabric_generator/verilog_output
-MAX_BITBYTES=16384
 
 rm -rf tmp
 mkdir tmp
 for i in $(find ../Tile -type f -name "*.v") $(find ../Fabric -type f -name "*.v")
-do 
+do
     cp $i tmp/
 done
 
-iverilog -D EMULATION -s fab_tb -o fab_tb.vvp test_design/${DESIGN}.vh tmp/* test_design/${DESIGN}.v fabulous_tb.v 
+iverilog -D EMULATION -s fab_tb -o fab_tb.vvp test_design/${DESIGN}.vh tmp/* test_design/${DESIGN}.v fabulous_tb.v
 vvp fab_tb.vvp
-rm -rf tmp
+rm -rf tmp

FABulous/fabric_files/FABulous_project_template_verilog/Test/run_simulation.sh

@@ -2,17 +2,16 @@
 set -ex
 DESIGN=counter
 BITSTREAM=test_design/${DESIGN}.bin
-VERILOG=../../fabric_generator/verilog_output
 MAX_BITBYTES=16384
 
 rm -rf tmp
 mkdir tmp
 for i in $(find ../Tile -type f -name "*.v") $(find ../Fabric -type f -name "*.v")
-do 
+do
     cp $i tmp/
 done
 
-iverilog -s fab_tb -o fab_tb.vvp tmp/* test_design/${DESIGN}.v fabulous_tb.v 
+iverilog -s fab_tb -o fab_tb.vvp tmp/* test_design/${DESIGN}.v fabulous_tb.v
 python3 makehex.py $BITSTREAM $MAX_BITBYTES bitstream.hex
 vvp fab_tb.vvp
-rm -rf tmp
+rm -rf tmp