rename and update for vhdl

FPGA-Research · Oct 25, 2024 · 160feab · 160feab
1 parent aefb18e
commit 160feab
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diff --git a/FABulous/fabric_files/FABulous_project_template_verilog/Fabric/models_pack.v b/FABulous/fabric_files/FABulous_project_template_verilog/Fabric/models_pack.v
@@ -192,7 +192,7 @@ module cus_mux41_buf (A0, A1, A2, A3, S0, S0N, S1, S1N, X);
 	assign X =  S1 ? B1 : B0;
 endmodule
 
-module cus_mux21_buf (A0, A1, S, X);
+module cus_mux21 (A0, A1, S, X);
 	input A0;
 	input A1;
 	input S;