Refactor file paths and imports in FABulous code

FABulous.py

@@ -15,11 +15,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
 from contextlib import redirect_stdout
-from fabric_generator.utilities import genFabricObject, GetFabric
-import fabric_generator.model_generation_npnr as model_gen_npnr
-from fabric_generator.code_generation_VHDL import VHDLWriter
-from fabric_generator.code_generation_Verilog import VerilogWriter
-from FABulous_API import FABulous
+from FABulous.fabric_code_generator.utilities import genFabricObject, GetFabric
+import FABulous.fabric_cad.model_generation_npnr as model_gen_npnr
+from FABulous.fabric_code_generator.code_generation_VHDL import VHDLWriter
+from FABulous.fabric_code_generator.code_generation_Verilog import VerilogWriter
+from FABulous.FABulous_API import FABulous
 import csv
 from glob import glob
 import os
@@ -926,7 +926,7 @@ def do_gen_bitStream_binary(self, args):
         logger.info(f"Outputting to {self.projectDir}/{parent}/{bitstream_file}")
         runCmd = [
             "python3",
-            f"{fabulousRoot}/fabric_cad/bit_gen.py",
+            f"{fabulousRoot}/FABulous/fabric_cad/bit_gen.py",
             "-genBitstream",
             f"{self.projectDir}/{parent}/{fasm_file}",
             f"{self.projectDir}/.FABulous/bitStreamSpec.bin",

FABulous_API.py → FABulous/FABulous_API.py

@@ -1,11 +1,11 @@
-import fabric_generator.model_generation_vpr as model_gen_vpr
-import fabric_generator.model_generation_npnr as model_gen_npnr
-from fabric_generator.code_generation_VHDL import VHDLWriter
-import fabric_generator.code_generator as codeGen
-import fabric_generator.file_parser as fileParser
-from fabric_generator.fabric import Fabric, Tile
-from fabric_generator.fabric_gen import FabricGenerator
-from geometry_generator.geometry_gen import GeometryGenerator
+import FABulous.fabric_cad.model_generation_vpr as model_gen_vpr
+import FABulous.fabric_cad.model_generation_npnr as model_gen_npnr
+from FABulous.fabric_code_generator.code_generation_VHDL import VHDLWriter
+import FABulous.fabric_code_generator.code_generator as codeGen
+import FABulous.fabric_code_generator.file_parser as fileParser
+from FABulous.fabric_definition.Fabric import Fabric
+from FABulous.fabric_code_generator.fabric_gen import FabricGenerator
+from FABulous.geometry_generator.geometry_gen import GeometryGenerator
 
 import logging
 

fabric_generator/model_generation_npnr.py → FABulous/fabric_cad/model_generation_npnr.py

@@ -1,8 +1,9 @@
 import string
 from typing import Tuple
-from fabric_generator.utilities import *
-from fabric_generator.fabric import Fabric, Tile
-from fabric_generator.file_parser import parseMatrix, parseList
+from ..fabric_code_generator.utilities import *
+from ..fabric_definition.Fabric import Fabric
+from ..fabric_definition.Tile import Tile
+from ..fabric_code_generator.file_parser import parseMatrix, parseList
 
 
 def genNextpnrModel(fabric: Fabric):

fabric_generator/model_generation_vpr.py → FABulous/fabric_cad/model_generation_vpr.py

@@ -1,13 +1,12 @@
 import string
-from sys import prefix
-from typing import List
-from fabric_generator.fabric_gen import FabricGenerator
-from fabric_generator.utilities import *
-from fabric_generator.fabric import IO, Bel, Fabric
+from ..fabric_code_generator.fabric_gen import FabricGenerator
+from ..fabric_code_generator.utilities import *
+from ..fabric_definition.Fabric import Fabric
+from ..fabric_definition.Bel import Bel
+from ..fabric_definition.defines import IO
+
 import xml.etree.ElementTree as ET
-import os
-from xml.dom import minidom
-from fabric_generator.file_parser import parseMatrix, parseList
+from ..fabric_code_generator.file_parser import parseMatrix, parseList
 import logging
 
 logger = logging.getLogger(__name__)

fabric_generator/code_generation_VHDL.py → FABulous/fabric_code_generator/code_generation_VHDL.py

@@ -1,11 +1,8 @@
-from typing import Literal, Tuple
-import os
 import math
 import re
 
-from fabric_generator.fabric import Fabric, Tile, Port, Bel, IO
-from fabric_generator.code_generator import codeGenerator
-from fabric_generator.fabric import ConfigBitMode
+from .code_generator import codeGenerator
+from ..fabric_definition.defines import IO
 
 
 class VHDLWriter(codeGenerator):

fabric_generator/code_generation_Verilog.py → FABulous/fabric_code_generator/code_generation_Verilog.py

@@ -1,9 +1,8 @@
-from typing import Literal
 import math
 import re
 
-from fabric_generator.fabric import Tile, Bel, ConfigBitMode, IO
-from fabric_generator.code_generator import codeGenerator
+from .code_generator import codeGenerator
+from ..fabric_definition.defines import IO
 
 
 class VerilogWriter(codeGenerator):

fabric_generator/code_generator.py → FABulous/fabric_code_generator/code_generator.py

@@ -1,6 +1,5 @@
 import abc
-from typing import List, Tuple
-from fabric_generator.fabric import Bel, IO, ConfigBitMode
+from ..fabric_definition.defines import IO
 
 
 class codeGenerator(abc.ABC):
@@ -313,9 +312,9 @@ def addInstantiation(
         self,
         compName: str,
         compInsName: str,
-        portsPairs: List[Tuple[str, str]],
-        paramPairs: List[Tuple[str, str]] = [],
-        emulateParamPairs: List[Tuple[str, str]] = [],
+        portsPairs: list[tuple[str, str]],
+        paramPairs: list[tuple[str, str]] = [],
+        emulateParamPairs: list[tuple[str, str]] = [],
         indentLevel=0,
     ):
         """
@@ -351,11 +350,11 @@ def addInstantiation(
         Args:
             compName (str): name of the component
             compInsName (str): name of the component instance
-            compPorts (List[str]): list of ports of the component
-            signals (List[str]): list of signals of the component
-            paramPorts (List[str], optional): list of parameter ports of the component. Defaults to [].
-            paramSignals (List[str], optional): list of parameter signals of the component. Defaults to [].
-            emulateParamPairs (List[str], optional): list of parameter signals of the component in emulation mode only. Defaults to [].
+            compPorts (list[str]): list of ports of the component
+            signals (list[str]): list of signals of the component
+            paramPorts (list[str], optional): list of parameter ports of the component. Defaults to [].
+            paramSignals (list[str], optional): list of parameter signals of the component. Defaults to [].
+            emulateParamPairs (list[str], optional): list of parameter signals of the component in emulation mode only. Defaults to [].
             indentLevel (int, optional): The indentation Level. Defaults to 0.
 
         Raises:

fabric_generator/fabric_gen.py → FABulous/fabric_code_generator/fabric_gen.py

@@ -21,20 +21,23 @@
 import os
 import string
 import csv
-from typing import Dict, List, Tuple
 import logging
 from pathlib import Path
 
 
 from fasm import *  # Remove this line if you do not have the fasm library installed and will not be generating a bitstream
 
 
-from fabric_generator.file_parser import parseMatrix, parseConfigMem, parseList
-from fabric_generator.fabric import IO, Direction, MultiplexerStyle, ConfigBitMode
-from fabric_generator.fabric import Fabric, Tile, Port, SuperTile, ConfigMem
-from fabric_generator.code_generation_VHDL import VHDLWriter
-from fabric_generator.code_generation_Verilog import VerilogWriter
-from fabric_generator.code_generator import codeGenerator
+from .file_parser import parseMatrix, parseConfigMem, parseList
+from ..fabric_definition.defines import IO, Direction, MultiplexerStyle, ConfigBitMode
+from ..fabric_definition.Fabric import Fabric
+from ..fabric_definition.Tile import Tile
+from ..fabric_definition.ConfigMem import ConfigMem
+from ..fabric_definition.SuperTile import SuperTile
+
+from .code_generation_VHDL import VHDLWriter
+from .code_generation_Verilog import VerilogWriter
+from .code_generator import codeGenerator
 
 SWITCH_MATRIX_DEBUG_SIGNAL = True
 logger = logging.getLogger(__name__)
@@ -297,7 +300,7 @@ def generateConfigMem(self, tile: Tile, configMemCsv: str) -> None:
 
         # test if we have a bitstream mapping file
         # if not, we will take the default, which was passed on from  GenerateConfigMemInit
-        configMemList: List[ConfigMem] = []
+        configMemList: list[ConfigMem] = []
         if os.path.exists(configMemCsv):
             logger.info(
                 f"Found bitstream mapping file {tile.name}_configMem.csv for tile {tile.name}"
@@ -420,7 +423,7 @@ def genTileSwitchMatrix(self, tile: Tile) -> None:
         """
 
         # convert the matrix to a dictionary map and performs entry check
-        connections: Dict[str, List[str]] = {}
+        connections: dict[str, list[str]] = {}
         if tile.matrixDir.endswith(".csv"):
             connections = parseMatrix(tile.matrixDir, tile.name)
         elif tile.matrixDir.endswith(".list"):
@@ -432,7 +435,7 @@ def genTileSwitchMatrix(self, tile: Tile) -> None:
             self.bootstrapSwitchMatrix(tile, matrixDir)
             self.list2CSV(tile.matrixDir, matrixDir)
             logger.info(
-                f"Update matrix directory to {matrixDir} for Fabric Tile Dictionary"
+                f"Update matrix directory to {matrixDir} for Fabric Tile dictionary"
             )
             tile.matrixDir = matrixDir
             connections = parseMatrix(tile.matrixDir, tile.name)
@@ -1686,10 +1689,10 @@ def generateFabric(self) -> None:
         # Tile instantiations
         for y, row in enumerate(self.fabric.tile):
             for x, tile in enumerate(row):
-                tilePortList: List[str] = []
-                tilePortsInfo: List[Tuple[List[Port], int, int]] = []
+                tilePortList: list[str] = []
+                tilePortsInfo: list[tuple[list[Port], int, int]] = []
                 outputSignalList = []
-                tileLocationOffset: List[Tuple[int, int]] = []
+                tileLocationOffset: list[tuple[int, int]] = []
                 superTileLoc = []
                 superTile = None
                 if tile == None:
@@ -2335,7 +2338,7 @@ def split_port(p):
         self.writer.addDesignDescriptionEnd()
         self.writer.writeToFile()
 
-    def generateBitsStreamSpec(self) -> Dict[str, Dict]:
+    def generateBitsStreamSpec(self) -> dict[str, dict]:
         """
         Generate the bits stream specification of the fabric. This is need and will be further parsed by the bit_gen.py
 
@@ -2364,7 +2367,7 @@ def generateBitsStreamSpec(self) -> Dict[str, Dict]:
                     tileMap[f"X{x}Y{y}"] = "NULL"
 
         specData["TileMap"] = tileMap
-        configMemList: List[ConfigMem] = []
+        configMemList: list[ConfigMem] = []
         for y, row in enumerate(self.fabric.tile):
             for x, tile in enumerate(row):
                 if tile == None:
@@ -2382,7 +2385,7 @@ def generateBitsStreamSpec(self) -> Dict[str, Dict]:
                     )
                     exit(-1)
 
-                encodeDict = [-1] * (
+                encodedict = [-1] * (
                     self.fabric.maxFramesPerCol * self.fabric.frameBitsPerRow
                 )
                 maskDic = {}
@@ -2392,7 +2395,7 @@ def generateBitsStreamSpec(self) -> Dict[str, Dict]:
                     # bit 0 in bit mask is the first value in the configBitRanges
                     for i, char in enumerate(cfm.usedBitMask):
                         if char == "1":
-                            encodeDict[cfm.configBitRanges.pop(0)] = (
+                            encodedict[cfm.configBitRanges.pop(0)] = (
                                 self.fabric.frameBitsPerRow - 1 - i
                             ) + self.fabric.frameBitsPerRow * cfm.frameIndex
 
@@ -2411,21 +2414,21 @@ def generateBitsStreamSpec(self) -> Dict[str, Dict]:
                 curTileMapNoMask = {}
 
                 for i, bel in enumerate(tile.bels):
-                    for featureKey, keyDict in bel.belFeatureMap.items():
-                        for entry in keyDict:
+                    for featureKey, keydict in bel.belFeatureMap.items():
+                        for entry in keydict:
                             if isinstance(entry, int):
-                                for v in keyDict[entry]:
+                                for v in keydict[entry]:
                                     curTileMap[
                                         f"{string.ascii_uppercase[i]}.{featureKey}"
                                     ] = {
-                                        encodeDict[curBitOffset + v]: keyDict[entry][v]
+                                        encodedict[curBitOffset + v]: keydict[entry][v]
                                     }
                                     curTileMapNoMask[
                                         f"{string.ascii_uppercase[i]}.{featureKey}"
                                     ] = {
-                                        encodeDict[curBitOffset + v]: keyDict[entry][v]
+                                        encodedict[curBitOffset + v]: keydict[entry][v]
                                     }
-                                curBitOffset += len(keyDict[entry])
+                                curBitOffset += len(keydict[entry])
 
                 # All the generation will be working on the tile level with the tileDic
                 # This is added to propagate the updated switch matrix to each of the tile in the fabric
@@ -2449,9 +2452,9 @@ def generateBitsStreamSpec(self) -> Dict[str, Dict]:
                                 curTileMap[pip] = {}
                                 curTileMapNoMask[pip] = {}
 
-                            curTileMap[pip][encodeDict[curBitOffset + c]] = curChar
+                            curTileMap[pip][encodedict[curBitOffset + c]] = curChar
                             curTileMapNoMask[pip][
-                                encodeDict[curBitOffset + c]
+                                encodedict[curBitOffset + c]
                             ] = curChar
 
                     curBitOffset += controlWidth