fpga: Change default burst for xilinx ips #34

CyrilKoe · 2024-07-15T07:11:40Z

When using certain Xilinx IPs, the burst type FIXED is not supported. In practice, they are not used (len=0) anyways.

AXI SmartConnect product guide (PG247):

SmartConnect does not support FIXED type bursts. Any FIXED burst transaction received at the SmartConnect SI is blocked and a DECERR response is returned to the master.

Removing one problematic parameter (should not be Resp=RESP_OKAY in the axi error slave) Redefining the pop signal for a FIFO, which was faultly popping data from an empty FIFO, activating the assertions.

Included the assert header into the regmap file requiring the ASSERT macros.

Your Name and others added 8 commits May 23, 2024 13:48

Introduce bender and fix some versioning mismatch.

304ffc6

Fixing compile errors.

6dc10ac

Removing one problematic parameter (should not be Resp=RESP_OKAY in the axi error slave) Redefining the pop signal for a FIFO, which was faultly popping data from an empty FIFO, activating the assertions.

Fixing an error on msiptw reported by Synopsys DC

b090ead

Fixing mismatch with apb2reg and DC compiler errors.

906c72d

Renaming apb_to_reg to avoid conflicts

e2dc8ab

Add include dir in bender manifest to fetch ASSERTs.

c9c50f4

Included the assert header into the regmap file requiring the ASSERT macros.

Reintroduce the Assert calls.

26ae5a8

fpga: Change default burst for xilinx ips

58654e0

maicolciani force-pushed the pulp branch from 26ae5a8 to 41da12d Compare July 31, 2024 10:10

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fpga: Change default burst for xilinx ips #34

fpga: Change default burst for xilinx ips #34

CyrilKoe commented Jul 15, 2024

fpga: Change default burst for xilinx ips #34

Are you sure you want to change the base?

fpga: Change default burst for xilinx ips #34

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CyrilKoe commented Jul 15, 2024