Reintroduce the Assert calls.

zero-day-labs · Jul 31, 2024 · 41da12d · 41da12d
1 parent de1f4fe
commit 41da12d
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Showing 2 changed files with 3 additions and 4 deletions.
diff --git a/rtl/riscv_iommu.sv b/rtl/riscv_iommu.sv
@@ -774,11 +774,10 @@ module riscv_iommu #(
             .ar_chan_t      ( ar_chan_t     ),
             .r_chan_t       ( r_chan_t      ),
             // AXI request/response
-            .req_t          ( axi_req_t     ),
-            .resp_t         ( axi_rsp_t     ),
+            .axi_req_t      ( axi_req_t     ),
+            .axi_resp_t     ( axi_rsp_t     ),
             .NoMstPorts     ( 2             ),  // MRIF supports adds ignoring mechanism
             .AxiLookBits    ( ID_WIDTH      ),  // Assuming same value as AXI ID width
-            .FallThrough    ( 1'b0          ),
             .SpillAw        ( 1'b0          ),
             .SpillW         ( 1'b0          ),
             .SpillB         ( 1'b0          ),

diff --git a/rtl/software_interface/regmap/rv_iommu_regmap.sv b/rtl/software_interface/regmap/rv_iommu_regmap.sv
@@ -3545,6 +3545,6 @@ module rv_iommu_regmap #(
   assign unused_be = ^reg_be;
 
   // Assertions for Register Interface
-  // `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
 
 endmodule