HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.
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Mar 8, 2024 - C++
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superscalar-cpu
Here are 8 public repositories matching this topic...
Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture
microprocessor perceptron computer-architecture superscalar branch-prediction portland-state-university simplescalar-simulator simple-scalar ss3 superscalar-cpu perceptron-branch-prediction combinational-branch-prediction
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Mar 24, 2024 - C
Instructions Per Count (IPC) Study on 9-Stage Supescalar Pipeline with Out-of-Order Execution
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Mar 23, 2023 - C++
Implementation of a Superscalar CPU with Dynamic Scheduling which support RISC-V standard ISA with standard 'M' Extention
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Oct 20, 2021
ECE552: Computer Architecture — Fall 2020.
multithreading computer-architecture branch-prediction cache-coherence cache-optimization instruction-level-parallelism memory-consistency dynamic-scheduling control-hazards data-hazards multiprocessor-systems superscalar-cpu
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Dec 28, 2021 - C
Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay
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Dec 13, 2022 - VHDL
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
processor-architecture fpga processor out-of-order superscalar risc-v processor-simulator ddr3 processor-design axi4 superscalar-cpu
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Oct 7, 2024 - SystemVerilog
A simple cpu simulator and an analyisis of its performance.
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Oct 4, 2023 - Python
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