SuperScalar CPU with Dynamic shceduling

Design & implementation by Group 2
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Table of Contents

1. About The Project
2. License
3. Contact
4. Acknowledgements

About The Project

Implementation of a Superscalar CPU with Dynamic Scheduling which support RISC-V standard ISA with standard 'M' Extention.

License

Distributed under the MIT License. See LICENSE for more information.

Contact

Isuru Lakshan - @isuru - email

Randika viraj - @randika - email

Project Link: https://github.com/cepdnaclk/e16-Co502-SuperScalar-CPU-With-Dynamic-Sheduling

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Acknowledgements

• Dr. Isuru Nawinne
• Dr. Mahanama Wickramasinghe