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checkpatch.yml
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target/riscv: Adding register tables to make register names consiste Check Code Style (checkpatch) #685: Pull request #896 synchronize by AnastasiyaChernikova
October 12, 2023 11:49 35s AnastasiyaChernikova:ac-sc2
AnastasiyaChernikova:ac-sc2
October 12, 2023 11:49 35s
target/riscv: cache requests to trigger configuration Check Code Style (checkpatch) #681: Pull request #928 synchronize by AnastasiyaChernikova
October 12, 2023 08:10 44s AnastasiyaChernikova:triggers
AnastasiyaChernikova:triggers
October 12, 2023 08:10 44s
server/gdb_server: Handle events if first target is unavailable Check Code Style (checkpatch) #680: Pull request #926 synchronize by timsifive
October 10, 2023 17:57 46s unavailable_events
unavailable_events
October 10, 2023 17:57 46s
gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not imple… Check Code Style (checkpatch) #679: Pull request #925 synchronize by timsifive
October 10, 2023 17:51 34s unavailable_reg
unavailable_reg
October 10, 2023 17:51 34s
target/riscv: use cacheable read/write function to handle DCSR Check Code Style (checkpatch) #678: Pull request #920 synchronize by lz-bro
October 7, 2023 01:31 41s lz-bro:dcsr-cachable
lz-bro:dcsr-cachable
October 7, 2023 01:31 41s
do not assume DTM version unless dtmcontrol is read successfully Check Code Style (checkpatch) #677: Pull request #929 synchronize by aap-sc
October 6, 2023 15:52 36s aap-sc:riscv
aap-sc:riscv
October 6, 2023 15:52 36s
target/riscv: Adding register tables to make register names consiste Check Code Style (checkpatch) #676: Pull request #896 synchronize by AnastasiyaChernikova
October 5, 2023 16:12 32s AnastasiyaChernikova:ac-sc2
AnastasiyaChernikova:ac-sc2
October 5, 2023 16:12 32s