Step Five: Finishing up the Execute Unit

Step Five: Finishing up the Execute Unit

Now that the instruction decoder, register file, and ALU have been built, the only remaining component of the execute stage is the branch unit. The branch unit calculates the address of the next instruction to be executed by either incrementing the current address, or adding the immediate value decoded by the instruction decoder to the current address. This is done by using two adders and a multiplexer; the input to the multiplexer is a logical and of the ALU comparison result and the signal is_branch:

library ieee;
use ieee.std_logic_1164.all;

entity branch_unit is
   port (res       : in  std_logic;
         is_branch : in  std_logic;
         imm       : in  std_logic_vector (7 downto 0);
         pc_in     : in  std_logic_vector (15 downto 0);
         pc_out    : out std_logic_vector (15 downto 0));
end branch_unit;
architecture structural of branch_unit is
   signal pc_in_plus_imm, pc_in_plus_2, imm16 : std_logic_vector (15 downto 0) := (others => '0');

   component adder is
      generic(dwidth : positive);
      port (a : in  std_logic_vector (dwidth-1 downto 0);
            b : in  std_logic_vector (dwidth-1 downto 0) := (dwidth-1 downto 2 => '0') & "10";
            s : out std_logic_vector (dwidth-1 downto 0));
   end component;

begin

   pc_out <=   pc_in_plus_imm when (is_branch = '1' and res = '1') else
               pc_in_plus_2;

   --pc + imm
   imm_add0 : adder generic map(dwidth => 16)
                       port map(a      => pc_in,
                                b      => imm16,
                                s      => pc_in_plus_imm);

   --pc + 2
   inc2_add0 : adder generic map(dwidth => 16)
                        port map(a      => pc_in,
                                 b      => open,
                                 s      => pc_in_plus_2);
   imm16 <= (15 downto 8 => imm(7)) & imm;
end structural;

pc_out is then fed into the instruction fetch unit's pc_in, and replaces the value in the program counter on the next rising clock edge.

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