An 8-bit data, 16-bit instruction load-store 2 pipeline stage CPU with 7 GPRs
muCPU - first vhdl version of the processor has only 3 gprs
muCPUv2 - second version
muCPUv2_1 - latest version (more memory, instructions)
The formatting of the VHDL code is messy (for some files) because the tab size is different for the IDE than it is for Github (add ?ts=3 to the end of the url when viewing the .vhd files). I've now switched my IDE to add spaces instead of tabs when I press "tab", so new files shouldn't have this problem.