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    41 repositories

    • mrisc32

      Public
      MRSIC32 ISA documentation and development
      TeX
      •
      Creative Commons Attribution Share Alike 4.0 International
      •9•0•0•0•Updated Jan 12, 2021Jan 12, 2021

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •792•0•0•0•Updated Nov 26, 2020Nov 26, 2020

    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      SystemVerilog
      •
      Apache License 2.0
      •555•0•0•0•Updated Nov 26, 2020Nov 26, 2020

    • rocket-chip

      Public
      Rocket Chip Generator
      Scala
      •
      Other
      •1.1k•0•0•0•Updated Nov 26, 2020Nov 26, 2020

    • fusesoc

      Public
      Package manager and build abstraction tool for FPGA/ASIC development
      Python
      •
      BSD 2-Clause "Simplified" License
      •249•0•0•0•Updated Nov 25, 2020Nov 25, 2020

    • VexRiscv

      Public
      A FPGA friendly 32 bit RISC-V CPU implementation
      Assembly
      •
      MIT License
      •421•0•0•0•Updated Nov 25, 2020Nov 25, 2020

    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      SystemVerilog
      •
      Other
      •706•0•0•0•Updated Nov 24, 2020Nov 24, 2020

    • RT-LIFE

      Public
      RT-LIFE: An Interface to easily attach Integrity Monitors to IoT-class processors
      Verilog
      •
      Other
      •2•0•0•0•Updated Nov 24, 2020Nov 24, 2020

    • orca-mpsoc

      Public
      This repository holds the hardware project for the ORCA MPSoC platform.
      VHDL
      •
      GNU General Public License v2.0
      •3•0•0•0•Updated Nov 21, 2020Nov 21, 2020

    • dromajo

      Public
      RISC-V RV64GC emulator designed for RTL co-simulation
      C++
      •
      Apache License 2.0
      •62•0•0•0•Updated Nov 19, 2020Nov 19, 2020

    • NyuziProcessor

      Public
      GPGPU microprocessor architecture
      C
      •
      Apache License 2.0
      •356•0•0•0•Updated Nov 16, 2020Nov 16, 2020

    • scr1

      Public
      SCR1 is a high-quality open-source RISC-V MCU core in Verilog
      SystemVerilog
      •
      Other
      •282•0•0•0•Updated Nov 15, 2020Nov 15, 2020

    • Cores-SweRVolf

      Public
      FuseSoC-based SoC for SweRV EH1
      Coq
      •68•0•0•0•Updated Nov 11, 2020Nov 11, 2020

    • FGPU

      Public
      FGPU is a soft GPU architecture general purpose computing
      VHDL
      •
      GNU General Public License v3.0
      •15•0•0•0•Updated Nov 9, 2020Nov 9, 2020

    • exactstep

      Public
      Instruction accurate instruction set simulator for RISC-V, MIPS and ARM-v6m
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •18•0•0•0•Updated Nov 8, 2020Nov 8, 2020

    • riscv_vhdl

      Public
      Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
      C++
      •
      Apache License 2.0
      •104•0•0•0•Updated Oct 5, 2020Oct 5, 2020

    • fusesoc-cores

      Public
      FuseSoC standard core library
      Verilog
      •35•0•0•0•Updated Sep 24, 2020Sep 24, 2020

    • biriscv

      Public
      32-bit Superscalar RISC-V CPU
      Verilog
      •
      Apache License 2.0
      •150•0•0•0•Updated Sep 21, 2020Sep 21, 2020

    • cleanflight

      Public
      Clean-code version of the baseflight flight controller firmware
      C
      •
      GNU General Public License v3.0
      •1.4k•0•0•0•Updated Sep 9, 2020Sep 9, 2020

    • sail-riscv

      Public
      Sail RISC-V model
      Coq
      •
      Other
      •171•0•0•0•Updated Aug 28, 2020Aug 28, 2020

    • f32c

      Public
      A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
      VHDL
      •
      BSD 2-Clause "Simplified" License
      •104•0•0•0•Updated Jul 23, 2020Jul 23, 2020

    • tacle-bench

      Public
      TACLe Benchmarks
      C
      •40•0•0•0•Updated Jun 26, 2020Jun 26, 2020

    • Open-GPGPU-FlexGrip-

      Public
      FlexGripPlus: an open-source GPGPU model for reliability evaluation and simulation
      Stata
      •18•0•0•0•Updated Jun 16, 2020Jun 16, 2020

    • orca-software-tools

      Public
      C
      •
      GNU Affero General Public License v3.0
      •4•0•0•0•Updated May 11, 2020May 11, 2020

    • orca-sim

      Public
      A Simulator for ORCA Platform made on top of URSA Engine.
      C++
      •
      GNU Affero General Public License v3.0
      •9•0•0•0•Updated May 7, 2020May 7, 2020

    • strassen-winograd

      Public
      Strassen and Winograd algorithms for efficient matrix multiplication
      riscvriscv-emulatororca-mpsocorca-sim
      C
      •4•1•0•0•Updated May 6, 2020May 6, 2020

    • lenet_cnn

      Public
      The convolutional neural network LeNet by Yann LeCun. This example tests the weights provided in 4 byte data type with smaller data types (short/ char) in order to test the implemetation in a micro-controller.
      cnnmnistlenetmpsocriscv32riscv-emulatororca-sim
      C
      •2•1•0•0•Updated May 6, 2020May 6, 2020

    • optimsoc

      Public
      OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
      C
      •
      Other
      •23•0•0•0•Updated May 4, 2020May 4, 2020

    • hellfireos

      Public
      HellfireOS Realtime Operating System
      C
      •
      GNU General Public License v2.0
      •31•0•0•0•Updated Mar 16, 2020Mar 16, 2020

    • swerv-ISS

      Public
      Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
      C++
      •
      GNU General Public License v3.0
      •41•0•0•0•Updated Jan 28, 2020Jan 28, 2020