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    21 repositories

    • .github

      Public
      1•0•0•1•Updated Dec 28, 2024Dec 28, 2024

    • open_eFPGA_v2

      Public
      Verilog
      •
      Apache License 2.0
      •2•4•0•0•Updated Dec 27, 2024Dec 27, 2024

    • FABulous_board

      Public
      A PCB created for FABulous FPGAs, based on the caravel board.
      pcbcaravelfpga-board
      Python
      •
      Apache License 2.0
      •0•0•2•0•Updated Dec 27, 2024Dec 27, 2024

    • FABulous

      Public
      Fabric generator and CAD tools
      Python
      •
      Apache License 2.0
      •36•151•34•7•Updated Dec 17, 2024Dec 17, 2024

    • FABulator

      Public
      Fabric generator and CAD tools graphical frontend
      Java
      •
      Apache License 2.0
      •3•7•7•0•Updated Mar 26, 2024Mar 26, 2024

    • GoAhead

      Public
      GoAhead
      C#
      •1•1•0•0•Updated Jun 14, 2023Jun 14, 2023

    • OrkhestraFPGAStream

      Public
      Private repository for accelerating DBMS SQL queries with FPGAs
      databasefpga
      C++
      •
      Apache License 2.0
      •1•5•6•0•Updated Feb 28, 2023Feb 28, 2023

    • nextpnr

      Public archive
      a fork of nextpnr for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream nextpnr
      C++
      •
      ISC License
      •247•1•0•0•Updated Dec 1, 2022Dec 1, 2022

    • byteman

      Public
      Bitstream relocation and manipulation tool.
      C++
      •
      Apache License 2.0
      •3•40•0•0•Updated Nov 29, 2022Nov 29, 2022

    • FPGA-VS-Web

      Public
      FPGA VIrus Scanner Web Application
      JavaScript
      •0•0•1•0•Updated May 19, 2022May 19, 2022

    • FABulous-Sky---a-heterogeneous-FPGA-fabric-in-Skywater130

      Public
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •332•8•0•0•Updated Nov 19, 2021Nov 19, 2021

    • nextpnr-fabulous

      Public archive
      a fork of nextpnr for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream nextpnr
      C++
      •
      ISC License
      •1•3•0•0•Updated Aug 18, 2021Aug 18, 2021

    • fuserisc

      Public
      Dual RISC-V DISC with integrated eFPGA
      Verilog
      •
      Apache License 2.0
      •4•3•0•0•Updated Jul 16, 2021Jul 16, 2021

    • yosys

      Public archive
      Yosys Open SYnthesis Suite fork for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream yosys
      C++
      •
      ISC License
      •893•1•0•0•Updated Jun 28, 2021Jun 28, 2021

    • eFPGA---RTL-to-GDS-with-SKY130

      Public
      This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
      Verilog
      •
      Apache License 2.0
      •12•26•2•0•Updated Jun 2, 2021Jun 2, 2021

    • FABulous-SKY130

      Public
      Verilog
      •
      Apache License 2.0
      •2•4•1•0•Updated Apr 28, 2021Apr 28, 2021

    • FPGAVirusScanner

      Public
      Program to scan for malicious FPGA designs.
      Python
      •
      Other
      •4•13•0•1•Updated Mar 20, 2021Mar 20, 2021

    • fos

      Public
      FOS - FPGA Operating System
      VHDL
      •
      Other
      •11•61•1•0•Updated Oct 22, 2020Oct 22, 2020

    • XilinxTCL_utilities

      Public
      Tcl
      •1•1•1•0•Updated Sep 3, 2020Sep 3, 2020

    • zynq-ultrascale-readback-capture

      Public
      This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the same task to Zynq UltraScale+ MPSoC with several noticeable differences.
      Tcl
      •6•14•0•0•Updated Nov 15, 2019Nov 15, 2019

    • readdebugbitstream

      Public
      Python
      •0•0•0•0•Updated Feb 8, 2019Feb 8, 2019