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UTIL: Add riscv64 support #829

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Sep 8, 2023
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UTIL: Add riscv64 support #829

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1 change: 1 addition & 0 deletions src/Makefile.am
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,7 @@ noinst_HEADERS = \
coll_score/ucc_coll_score.h \
utils/arch/aarch64/cpu.h \
utils/arch/ppc64/cpu.h \
utils/arch/riscv64/cpu.h \
utils/arch/x86_64/cpu.h \
utils/arch/cpu.h \
utils/arch/cuda_def.h \
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6 changes: 6 additions & 0 deletions src/utils/arch/cpu.h
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Expand Up @@ -2,6 +2,7 @@
* Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2001-2023. ALL RIGHTS RESERVED.
* Copyright (C) ARM Ltd. 2016. ALL RIGHTS RESERVED.
* Copyright (C) Shanghai Zhaoxin Semiconductor Co., Ltd. 2020. ALL RIGHTS RESERVED.
* Copyright (C) Rivos Inc. 2023
*
* See file LICENSE for terms.
*/
Expand Down Expand Up @@ -44,6 +45,7 @@ typedef enum ucc_cpu_vendor {
UCC_CPU_VENDOR_AMD,
UCC_CPU_VENDOR_GENERIC_ARM,
UCC_CPU_VENDOR_GENERIC_PPC,
UCC_CPU_VENDOR_GENERIC_RISCV,
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UCC_CPU_VENDOR_FUJITSU_ARM,
UCC_CPU_VENDOR_ZHAOXIN,
UCC_CPU_VENDOR_LAST
Expand All @@ -59,6 +61,8 @@ static inline ucc_cpu_vendor_t ucc_get_vendor_from_str(const char *v_name)
return UCC_CPU_VENDOR_GENERIC_ARM;
if (strcasecmp(v_name, "ppc") == 0)
return UCC_CPU_VENDOR_GENERIC_PPC;
if (strcasecmp(v_name, "riscv") == 0)
return UCC_CPU_VENDOR_GENERIC_RISCV;
if (strcasecmp(v_name, "fujitsu") == 0)
return UCC_CPU_VENDOR_FUJITSU_ARM;
if (strcasecmp(v_name, "zhaoxin") == 0)
Expand Down Expand Up @@ -107,6 +111,8 @@ static inline ucc_cpu_model_t ucc_get_model_from_str(const char *m_name)
# include "ppc64/cpu.h"
#elif defined(__aarch64__)
# include "aarch64/cpu.h"
#elif defined(__riscv) && (__riscv_xlen == 64)
# include "riscv64/cpu.h"
#else
# error "Unsupported architecture"
#endif
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33 changes: 33 additions & 0 deletions src/utils/arch/riscv64/cpu.h
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@@ -0,0 +1,33 @@
/**
* Copyright (c) 2001-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (C) ARM Ltd. 2016-2017. ALL RIGHTS RESERVED.
* Copyright (C) Rivos Inc. 2023
*
* See file LICENSE for terms.
*/

#ifndef UCC_UTILS_ARCH_RISCV64_CPU_H_
#define UCC_UTILS_ARCH_RISCV64_CPU_H_

#define UCC_ARCH_CACHE_LINE_SIZE 64

/* RVWMO rules */
#define ucc_memory_bus_fence() asm volatile("fence iorw, iorw" ::: "memory")
#define ucc_memory_bus_store_fence() asm volatile("fence ow, ow" ::: "memory")
#define ucc_memory_bus_load_fence() asm volatile("fence ir, ir" ::: "memory")

#define ucc_memory_cpu_fence() asm volatile("fence rw, rw" ::: "memory")
#define ucc_memory_cpu_store_fence() asm volatile("fence rw, w" ::: "memory")
#define ucc_memory_cpu_load_fence() asm volatile("fence r, rw" ::: "memory")

static inline ucc_cpu_model_t ucc_arch_get_cpu_model()
{
return UCC_CPU_MODEL_UNKNOWN;
}

static inline ucc_cpu_vendor_t ucc_arch_get_cpu_vendor()
{
return UCC_CPU_VENDOR_GENERIC_RISCV;
}

#endif
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