merge dev into master #1026
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merge dev into master #1026
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…ger load followed by fpu instr
Adding formal rule for coverage holes on controller
RVFI - Correction corner case conflict on mstatus_fs upades when integer load followed by fpu instr
Updated jasper SLEC script for parameters usage. Added assumption files and bind file scripts/slec/cadence folder.
Added license headers
…. Uncommented the row4 trigger_match_i assertion from controller_assert file
jasper SLEC script changes
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
…nts. Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
RISC-V ISA Formal Verification setup and script files for Siemens Questa Processor tool
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Up-to-date files for RISC-V ISA Formal Verification.
Signed-off-by: Pascal Gouedo <[email protected]>
added 9 commits
July 3, 2024 18:17
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
User Manual final updates.
…-v-docs, cv32e40p, core-v-verif). Signed-off-by: Pascal Gouedo <[email protected]>
All links updated to cv32e40p_v1.8.3 tag for the 3 target repos (core-v-docs, cv32e40p, core-v-verif).
Signed-off-by: Pascal Gouedo <[email protected]>
core-v-docs changed to programs
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