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[L0] Interrupt-based event implementation #2334
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ad277f0
[L0] Interrupt-based event implementation
winstonzhang-intel 933760b
[L0] Fix urEnqueueEventsWaitWithBarrier option1
winstonzhang-intel 28e7d38
[L0] Cleaned up urEnqueueEventsWaitWithBarrier(Ext) with helper option
winstonzhang-intel d9576ca
[L0] Rebased against top of main
winstonzhang-intel 0856313
[L0] Interrupt-based event implementation
winstonzhang-intel f7fa435
[L0] Interrupt-based event implementation
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Original file line number | Diff line number | Diff line change |
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@@ -33,6 +33,24 @@ struct l0_command_list_cache_info { | |
bool IsImmediate = false; | ||
}; | ||
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typedef uint32_t ze_intel_event_sync_mode_exp_flags_t; | ||
typedef enum _ze_intel_event_sync_mode_exp_flag_t { | ||
ZE_INTEL_EVENT_SYNC_MODE_EXP_FLAG_LOW_POWER_WAIT = ZE_BIT(0), | ||
ZE_INTEL_EVENT_SYNC_MODE_EXP_FLAG_SIGNAL_INTERRUPT = ZE_BIT(1), | ||
ZE_INTEL_EVENT_SYNC_MODE_EXP_EXP_FLAG_FORCE_UINT32 = 0x7fffffff | ||
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} ze_intel_event_sync_mode_exp_flag_t; | ||
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#define ZE_INTEL_STRUCTURE_TYPE_EVENT_SYNC_MODE_EXP_DESC \ | ||
(ze_structure_type_t)0x00030016 | ||
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typedef struct _ze_intel_event_sync_mode_exp_desc_t { | ||
ze_structure_type_t stype; | ||
const void *pNext; | ||
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ze_intel_event_sync_mode_exp_flags_t syncModeFlags; | ||
} ze_intel_event_sync_mode_exp_desc_t; | ||
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struct ur_context_handle_t_ : _ur_object { | ||
ur_context_handle_t_(ze_context_handle_t ZeContext, uint32_t NumDevices, | ||
const ur_device_handle_t *Devs, bool OwnZeContext) | ||
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@@ -150,9 +168,9 @@ struct ur_context_handle_t_ : _ur_object { | |
// head. | ||
// | ||
// Cache of event pools to which host-visible events are added to. | ||
std::vector<std::list<ze_event_pool_handle_t>> ZeEventPoolCache{12}; | ||
std::vector<std::list<ze_event_pool_handle_t>> ZeEventPoolCache{30}; | ||
std::vector<std::unordered_map<ze_device_handle_t, size_t>> | ||
ZeEventPoolCacheDeviceMap{12}; | ||
ZeEventPoolCacheDeviceMap{30}; | ||
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// This map will be used to determine if a pool is full or not | ||
// by storing number of empty slots available in the pool. | ||
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@@ -208,13 +226,15 @@ struct ur_context_handle_t_ : _ur_object { | |
bool ProfilingEnabled, | ||
ur_device_handle_t Device, | ||
bool CounterBasedEventEnabled, | ||
bool UsingImmCmdList); | ||
bool UsingImmCmdList, | ||
bool InterruptBasedEventEnabled); | ||
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// Get ur_event_handle_t from cache. | ||
ur_event_handle_t getEventFromContextCache(bool HostVisible, | ||
bool WithProfiling, | ||
ur_device_handle_t Device, | ||
bool CounterBasedEventEnabled); | ||
bool CounterBasedEventEnabled, | ||
bool InterruptBasedEventEnabled); | ||
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// Add ur_event_handle_t to cache. | ||
void addEventToContextCache(ur_event_handle_t); | ||
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@@ -225,17 +245,29 @@ struct ur_context_handle_t_ : _ur_object { | |
HostVisibleCounterBasedRegularCacheType, | ||
HostInvisibleCounterBasedRegularCacheType, | ||
HostVisibleCounterBasedImmediateCacheType, | ||
HostInvisibleCounterBasedImmediateCacheType | ||
HostInvisibleCounterBasedImmediateCacheType, | ||
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HostVisibleInterruptBasedRegularCacheType, | ||
HostInvisibleInterruptBasedRegularCacheType, | ||
HostVisibleInterruptBasedImmediateCacheType, | ||
HostInvisibleInterruptBasedImmediateCacheType, | ||
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HostVisibleInterruptAndCounterBasedRegularCacheType, | ||
HostInvisibleInterruptAndCounterBasedRegularCacheType, | ||
HostVisibleInterruptAndCounterBasedImmediateCacheType, | ||
HostInvisibleInterruptAndCounterBasedImmediateCacheType | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This is exactly why I've asked you to do the refactor. This will grow exponentially with new event parameters. |
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}; | ||
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std::list<ze_event_pool_handle_t> * | ||
getZeEventPoolCache(bool HostVisible, bool WithProfiling, | ||
bool CounterBasedEventEnabled, bool UsingImmediateCmdList, | ||
bool InterruptBasedEventEnabled, | ||
ze_device_handle_t ZeDevice) { | ||
EventPoolCacheType CacheType; | ||
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calculateCacheIndex(HostVisible, CounterBasedEventEnabled, | ||
UsingImmediateCmdList, CacheType); | ||
UsingImmediateCmdList, InterruptBasedEventEnabled, | ||
CacheType); | ||
if (ZeDevice) { | ||
auto ZeEventPoolCacheMap = | ||
WithProfiling ? &ZeEventPoolCacheDeviceMap[CacheType * 2] | ||
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@@ -255,23 +287,57 @@ struct ur_context_handle_t_ : _ur_object { | |
ur_result_t calculateCacheIndex(bool HostVisible, | ||
bool CounterBasedEventEnabled, | ||
bool UsingImmediateCmdList, | ||
bool InterruptBasedEventEnabled, | ||
EventPoolCacheType &CacheType) { | ||
if (CounterBasedEventEnabled && HostVisible && !UsingImmediateCmdList) { | ||
CacheType = HostVisibleCounterBasedRegularCacheType; | ||
} else if (CounterBasedEventEnabled && !HostVisible && | ||
!UsingImmediateCmdList) { | ||
CacheType = HostInvisibleCounterBasedRegularCacheType; | ||
} else if (CounterBasedEventEnabled && HostVisible && | ||
UsingImmediateCmdList) { | ||
CacheType = HostVisibleCounterBasedImmediateCacheType; | ||
} else if (CounterBasedEventEnabled && !HostVisible && | ||
UsingImmediateCmdList) { | ||
CacheType = HostInvisibleCounterBasedImmediateCacheType; | ||
} else if (!CounterBasedEventEnabled && HostVisible) { | ||
CacheType = HostVisibleCacheType; | ||
if (InterruptBasedEventEnabled) { | ||
if (CounterBasedEventEnabled) { | ||
if (HostVisible) { | ||
if (UsingImmediateCmdList) { | ||
CacheType = HostVisibleInterruptAndCounterBasedImmediateCacheType; | ||
} else { | ||
CacheType = HostVisibleInterruptAndCounterBasedRegularCacheType; | ||
} | ||
} else { | ||
if (UsingImmediateCmdList) { | ||
CacheType = HostInvisibleInterruptAndCounterBasedImmediateCacheType; | ||
} else { | ||
CacheType = HostInvisibleInterruptAndCounterBasedRegularCacheType; | ||
} | ||
} | ||
} else { | ||
if (HostVisible) { | ||
if (UsingImmediateCmdList) { | ||
CacheType = HostVisibleInterruptBasedImmediateCacheType; | ||
} else { | ||
CacheType = HostVisibleInterruptBasedRegularCacheType; | ||
} | ||
} else { | ||
if (UsingImmediateCmdList) { | ||
CacheType = HostInvisibleInterruptBasedImmediateCacheType; | ||
} else { | ||
CacheType = HostInvisibleInterruptBasedRegularCacheType; | ||
} | ||
} | ||
} | ||
} else { | ||
CacheType = HostInvisibleCacheType; | ||
if (CounterBasedEventEnabled && HostVisible && !UsingImmediateCmdList) { | ||
CacheType = HostVisibleCounterBasedRegularCacheType; | ||
} else if (CounterBasedEventEnabled && !HostVisible && | ||
!UsingImmediateCmdList) { | ||
CacheType = HostInvisibleCounterBasedRegularCacheType; | ||
} else if (CounterBasedEventEnabled && HostVisible && | ||
UsingImmediateCmdList) { | ||
CacheType = HostVisibleCounterBasedImmediateCacheType; | ||
} else if (CounterBasedEventEnabled && !HostVisible && | ||
UsingImmediateCmdList) { | ||
CacheType = HostInvisibleCounterBasedImmediateCacheType; | ||
} else if (!CounterBasedEventEnabled && HostVisible) { | ||
CacheType = HostVisibleCacheType; | ||
} else { | ||
CacheType = HostInvisibleCacheType; | ||
} | ||
} | ||
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return UR_RESULT_SUCCESS; | ||
} | ||
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This will not work unless the interrupt based events are somehow first on the Cache container. The same is true of the counter-based events. There needs to be separate pool for interrupt-driven events (or maybe they shouldn't be cached at all?).