Updated readme and linting error

Signed-off-by: Anderson Ignacio <[email protected]>

README.md

@@ -17,7 +17,7 @@ AXI DMA is a general purpose direct memory access IP using [AXI4 AMBA](https://d
 - AXI4-Lite `Slave` interface to program the CSRs (Control and Status registers)
 - AXI4 `Master` interface to fetch/read and write data
 - Support for unaligned xfers (see below)
-- Configurable number of descriptors (default to 5)
+- Configurable number of descriptors (default to 2)
 - Abort processing available
 - Transfers up to 4GB of data per descriptor
 - Two modes of data access, **Fixed** [FIFO] and **Incremental**
@@ -36,7 +36,7 @@ Once finished, you should be able to open the logs and the generated waveforms a
 
 ### <a name="testlist"></a> Test list
 
-Here is listed all the tests that were implemented to check the DMA features. Although it does not check all possible combinations, it covers most of the basic usage and possible options. The `variants` are the additional runs of the same tests but with different scenarios like idle cycles and backpressure on the bus. For the `Flavors`, there are two types which 32b maps to `AXI_ADDR/DATA_WIDTH == 32 bits` and 64b to `AXI_ADDR_WIDTH == 32 bits` / `AXI_DATA_WIDTH == 64 bits`
+Here is listed all the tests that were implemented to check the DMA features. Although it does not check all possible combinations, it covers most of the basic usage and possible options. The `variants` are the additional runs of the same tests but with different scenarios like idle cycles and backpressure on the bus. For the `Flavors`, there are three types which 32b maps to `AXI_ADDR/DATA_WIDTH == 32 bits` and 64b to `AXI_ADDR_WIDTH == 32 bits` / `AXI_DATA_WIDTH == 64 bits`, the `small` flavor stands for a reduced dma 32b version with 8x beats burst, non-support for unaligned txns and no max burst control.
 
 | **No** |     **Test name**    |                  **Quick description**                 |             **Variants**            | **Flavor** |
 |:------:|:--------------------:|:------------------------------------------------------:|:-----------------------------------:|:----------:|
@@ -49,6 +49,7 @@ Here is listed all the tests that were implemented to check the DMA features. Al
 |    7   |    test_dma_modes    |   Check for the different running modes / INCR/FIXED   |                  --                 |   32b/64b  |
 |    8   |  test_dma_unaligned  | Test different unaligned addresses in the descriptors. |                  --                 |   32b/64b  |
 
+
 ## <a name="uarch"></a> Microarchitecture
 The `AXI DMA` microarchitecture is quite simple without anything complex to understand, the design is divided in two main flows, read and write data path. The block in violet is auto-generated using [Rggen](https://github.com/rggen/rggen) and it contains all the CSRs used and the other modules are original designs.
 ![rtl_uarch](docs/axi_dma.drawio.svg)

rtl/dma_streamer.sv

@@ -227,7 +227,7 @@ module dma_streamer
           // Best case, send as much as possible through a single txn
           // respecting the 4KB boundary and burst type INCR/FIXED
           next_dma_req.addr = aligned_addr(desc_addr_ff);
-          next_dma_req.size = (`DMA_DATA_WIDTH == 32) ? 2 : 3;
+          next_dma_req.size = (`DMA_DATA_WIDTH == 32) ? axi_size_t'(2) : axi_size_t'(3);
           next_dma_req.mode = dma_mode_ff;
 
           if (is_aligned(desc_addr_ff) && enough_for_burst(desc_bytes_ff)) begin

tb/test_dma_error.py

@@ -41,8 +41,8 @@ async def run_test(dut, config_clk="100MHz", idle_inserter=None, backpressure_in
     await tb.setup_clks(config_clk)
     await tb.rst(config_clk)
 
-    if (dma_flavor == "small"):
-        return True
+    # if (dma_flavor == "small"):
+        # return True
     #------------ Init test ------------#
     bb         = sim_settings['bb']
     max_data   = sim_settings['max_data']