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Added parameters to shrink the design size
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Signed-off-by: Anderson Ignacio <[email protected]>
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@aignacio
aignacio committed Oct 16, 2022
1 parent ad92d8e commit 34555cf
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Showing 13 changed files with 173 additions and 164 deletions.
Binary file modified csr_dma.xlsx
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60 changes: 30 additions & 30 deletions csr_out/csr_dma.h
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Original file line number Diff line number Diff line change
Expand Up @@ -47,38 +47,29 @@
#define CSR_DMA_DMA_DESC_SRC_ADDR_SRC_ADDR_BIT_MASK 0xffffffff
#define CSR_DMA_DMA_DESC_SRC_ADDR_SRC_ADDR_BIT_OFFSET 0
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_WIDTH 8
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_SIZE 40
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_SIZE 16
#define CSR_DMA_DMA_DESC_SRC_ADDR_ARRAY_DIMENSION 1
#define CSR_DMA_DMA_DESC_SRC_ADDR_ARRAY_SIZE_0 5
#define CSR_DMA_DMA_DESC_SRC_ADDR_ARRAY_SIZE_0 2
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_0 0x20
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_1 0x28
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_2 0x30
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_3 0x38
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_4 0x40
#define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_WIDTH 32
#define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_MASK 0xffffffff
#define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_OFFSET 0
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_WIDTH 8
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_SIZE 40
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_SIZE 16
#define CSR_DMA_DMA_DESC_DST_ADDR_ARRAY_DIMENSION 1
#define CSR_DMA_DMA_DESC_DST_ADDR_ARRAY_SIZE_0 5
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_0 0x48
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_1 0x50
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_2 0x58
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_3 0x60
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_4 0x68
#define CSR_DMA_DMA_DESC_DST_ADDR_ARRAY_SIZE_0 2
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_0 0x30
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_1 0x38
#define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_WIDTH 32
#define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_MASK 0xffffffff
#define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_OFFSET 0
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_WIDTH 8
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_SIZE 40
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_SIZE 16
#define CSR_DMA_DMA_DESC_NUM_BYTES_ARRAY_DIMENSION 1
#define CSR_DMA_DMA_DESC_NUM_BYTES_ARRAY_SIZE_0 5
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_0 0x70
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_1 0x78
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_2 0x80
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_3 0x88
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_4 0x90
#define CSR_DMA_DMA_DESC_NUM_BYTES_ARRAY_SIZE_0 2
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_0 0x40
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_1 0x48
#define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_WIDTH 1
#define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_MASK 0x1
#define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_OFFSET 0
Expand All @@ -89,23 +80,32 @@
#define CSR_DMA_DMA_DESC_CFG_ENABLE_BIT_MASK 0x1
#define CSR_DMA_DMA_DESC_CFG_ENABLE_BIT_OFFSET 2
#define CSR_DMA_DMA_DESC_CFG_BYTE_WIDTH 8
#define CSR_DMA_DMA_DESC_CFG_BYTE_SIZE 40
#define CSR_DMA_DMA_DESC_CFG_BYTE_SIZE 16
#define CSR_DMA_DMA_DESC_CFG_ARRAY_DIMENSION 1
#define CSR_DMA_DMA_DESC_CFG_ARRAY_SIZE_0 5
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_0 0x98
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_1 0xa0
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_2 0xa8
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_3 0xb0
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_4 0xb8
#define CSR_DMA_DMA_DESC_CFG_ARRAY_SIZE_0 2
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_0 0x50
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_1 0x58
typedef struct {
uint64_t dma_control;
uint64_t dma_status;
uint64_t dma_error_addr;
uint64_t dma_error_stats;
uint64_t dma_desc_src_addr[5];
uint64_t dma_desc_dst_addr[5];
uint64_t dma_desc_num_bytes[5];
uint64_t dma_desc_cfg[5];
uint64_t dma_desc_src_addr[2];
uint64_t dma_desc_dst_addr[2];
uint64_t dma_desc_num_bytes[2];
uint64_t dma_desc_cfg[2];
uint64_t __reserved_0x60;
uint64_t __reserved_0x68;
uint64_t __reserved_0x70;
uint64_t __reserved_0x78;
uint64_t __reserved_0x80;
uint64_t __reserved_0x88;
uint64_t __reserved_0x90;
uint64_t __reserved_0x98;
uint64_t __reserved_0xa0;
uint64_t __reserved_0xa8;
uint64_t __reserved_0xb0;
uint64_t __reserved_0xb8;
uint64_t __reserved_0xc0;
uint64_t __reserved_0xc8;
uint64_t __reserved_0xd0;
Expand Down
40 changes: 14 additions & 26 deletions csr_out/csr_dma.md
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Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,10 @@
|[dma_status](#csr_dma-dma_status)|0x08|
|[dma_error_addr](#csr_dma-dma_error_addr)|0x10|
|[dma_error_stats](#csr_dma-dma_error_stats)|0x18|
|[dma_desc_src_addr[5]](#csr_dma-dma_desc_src_addr)|0x20<br>0x28<br>0x30<br>0x38<br>0x40|
|[dma_desc_dst_addr[5]](#csr_dma-dma_desc_dst_addr)|0x48<br>0x50<br>0x58<br>0x60<br>0x68|
|[dma_desc_num_bytes[5]](#csr_dma-dma_desc_num_bytes)|0x70<br>0x78<br>0x80<br>0x88<br>0x90|
|[dma_desc_cfg[5]](#csr_dma-dma_desc_cfg)|0x98<br>0xa0<br>0xa8<br>0xb0<br>0xb8|
|[dma_desc_src_addr[2]](#csr_dma-dma_desc_src_addr)|0x20<br>0x28|
|[dma_desc_dst_addr[2]](#csr_dma-dma_desc_dst_addr)|0x30<br>0x38|
|[dma_desc_num_bytes[2]](#csr_dma-dma_desc_num_bytes)|0x40<br>0x48|
|[dma_desc_cfg[2]](#csr_dma-dma_desc_cfg)|0x50<br>0x58|

### <div id="csr_dma-dma_control"></div>dma_control

Expand Down Expand Up @@ -64,59 +64,47 @@
|error_src|[1]|ro|0x0||Error source - 0 READ / 1 WRITE|
|error_trig|[2]|ro|0x0||Error Trigger, asserted when error happens|

### <div id="csr_dma-dma_desc_src_addr"></div>dma_desc_src_addr[5]
### <div id="csr_dma-dma_desc_src_addr"></div>dma_desc_src_addr[2]

* offset_address
* 0x20
* 0x28
* 0x30
* 0x38
* 0x40
* type
* default

|name|bit_assignments|type|initial_value|reference|comment|
|:--|:--|:--|:--|:--|:--|
|src_addr|[31:0]|rw|0x00000000||Source address to fetch data|

### <div id="csr_dma-dma_desc_dst_addr"></div>dma_desc_dst_addr[5]
### <div id="csr_dma-dma_desc_dst_addr"></div>dma_desc_dst_addr[2]

* offset_address
* 0x48
* 0x50
* 0x58
* 0x60
* 0x68
* 0x30
* 0x38
* type
* default

|name|bit_assignments|type|initial_value|reference|comment|
|:--|:--|:--|:--|:--|:--|
|dst_addr|[31:0]|rw|0x00000000||Target address to write data|

### <div id="csr_dma-dma_desc_num_bytes"></div>dma_desc_num_bytes[5]
### <div id="csr_dma-dma_desc_num_bytes"></div>dma_desc_num_bytes[2]

* offset_address
* 0x70
* 0x78
* 0x80
* 0x88
* 0x90
* 0x40
* 0x48
* type
* default

|name|bit_assignments|type|initial_value|reference|comment|
|:--|:--|:--|:--|:--|:--|
|num_bytes|[31:0]|rw|0x00000000||Number of bytes to transfer|

### <div id="csr_dma-dma_desc_cfg"></div>dma_desc_cfg[5]
### <div id="csr_dma-dma_desc_cfg"></div>dma_desc_cfg[2]

* offset_address
* 0x98
* 0xa0
* 0xa8
* 0xb0
* 0xb8
* 0x50
* 0x58
* type
* default

Expand Down
36 changes: 18 additions & 18 deletions csr_out/csr_dma.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -41,20 +41,20 @@ module csr_dma
input logic i_dma_error_stats_error_type,
input logic i_dma_error_stats_error_src,
input logic i_dma_error_stats_error_trig,
output logic [4:0][31:0] o_dma_desc_src_addr_src_addr,
output logic [4:0][31:0] o_dma_desc_dst_addr_dst_addr,
output logic [4:0][31:0] o_dma_desc_num_bytes_num_bytes,
output logic [4:0] o_dma_desc_cfg_write_mode,
output logic [4:0] o_dma_desc_cfg_read_mode,
output logic [4:0] o_dma_desc_cfg_enable
output logic [1:0][31:0] o_dma_desc_src_addr_src_addr,
output logic [1:0][31:0] o_dma_desc_dst_addr_dst_addr,
output logic [1:0][31:0] o_dma_desc_num_bytes_num_bytes,
output logic [1:0] o_dma_desc_cfg_write_mode,
output logic [1:0] o_dma_desc_cfg_read_mode,
output logic [1:0] o_dma_desc_cfg_enable
);
rggen_register_if #(8, 64, 64) register_if[24]();
rggen_register_if #(8, 64, 64) register_if[12]();
rggen_axi4lite_adapter #(
.ID_WIDTH (ID_WIDTH),
.ADDRESS_WIDTH (ADDRESS_WIDTH),
.LOCAL_ADDRESS_WIDTH (8),
.BUS_WIDTH (64),
.REGISTERS (24),
.REGISTERS (12),
.PRE_DECODE (PRE_DECODE),
.BASE_ADDRESS (BASE_ADDRESS),
.BYTE_SIZE (256),
Expand Down Expand Up @@ -400,7 +400,7 @@ module csr_dma
end endgenerate
generate if (1) begin : g_dma_desc_src_addr
genvar i;
for (i = 0;i < 5;++i) begin : g
for (i = 0;i < 2;++i) begin : g
rggen_bit_field_if #(64) bit_field_if();
`rggen_tie_off_unused_signals(64, 64'h00000000ffffffff, bit_field_if)
rggen_default_register #(
Expand Down Expand Up @@ -447,21 +447,21 @@ module csr_dma
end endgenerate
generate if (1) begin : g_dma_desc_dst_addr
genvar i;
for (i = 0;i < 5;++i) begin : g
for (i = 0;i < 2;++i) begin : g
rggen_bit_field_if #(64) bit_field_if();
`rggen_tie_off_unused_signals(64, 64'h00000000ffffffff, bit_field_if)
rggen_default_register #(
.READABLE (1),
.WRITABLE (1),
.ADDRESS_WIDTH (8),
.OFFSET_ADDRESS (8'h48),
.OFFSET_ADDRESS (8'h30),
.BUS_WIDTH (64),
.DATA_WIDTH (64),
.REGISTER_INDEX (i)
) u_register (
.i_clk (i_clk),
.i_rst_n (i_rst_n),
.register_if (register_if[9+i]),
.register_if (register_if[6+i]),
.bit_field_if (bit_field_if)
);
if (1) begin : g_dst_addr
Expand Down Expand Up @@ -494,21 +494,21 @@ module csr_dma
end endgenerate
generate if (1) begin : g_dma_desc_num_bytes
genvar i;
for (i = 0;i < 5;++i) begin : g
for (i = 0;i < 2;++i) begin : g
rggen_bit_field_if #(64) bit_field_if();
`rggen_tie_off_unused_signals(64, 64'h00000000ffffffff, bit_field_if)
rggen_default_register #(
.READABLE (1),
.WRITABLE (1),
.ADDRESS_WIDTH (8),
.OFFSET_ADDRESS (8'h70),
.OFFSET_ADDRESS (8'h40),
.BUS_WIDTH (64),
.DATA_WIDTH (64),
.REGISTER_INDEX (i)
) u_register (
.i_clk (i_clk),
.i_rst_n (i_rst_n),
.register_if (register_if[14+i]),
.register_if (register_if[8+i]),
.bit_field_if (bit_field_if)
);
if (1) begin : g_num_bytes
Expand Down Expand Up @@ -541,21 +541,21 @@ module csr_dma
end endgenerate
generate if (1) begin : g_dma_desc_cfg
genvar i;
for (i = 0;i < 5;++i) begin : g
for (i = 0;i < 2;++i) begin : g
rggen_bit_field_if #(64) bit_field_if();
`rggen_tie_off_unused_signals(64, 64'h0000000000000007, bit_field_if)
rggen_default_register #(
.READABLE (1),
.WRITABLE (1),
.ADDRESS_WIDTH (8),
.OFFSET_ADDRESS (8'h98),
.OFFSET_ADDRESS (8'h50),
.BUS_WIDTH (64),
.DATA_WIDTH (64),
.REGISTER_INDEX (i)
) u_register (
.i_clk (i_clk),
.i_rst_n (i_rst_n),
.register_if (register_if[19+i]),
.register_if (register_if[10+i]),
.bit_field_if (bit_field_if)
);
if (1) begin : g_write_mode
Expand Down
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