Added DMA FSM and func wrapper

Signed-off-by: Anderson Ignacio <[email protected]>

.gitignore

@@ -32,3 +32,4 @@ output_temp/
 riscof_work/
 riscv-arch-test/
 ~$*
+docs/.**

csr_out/csr_dma.md

@@ -21,6 +21,7 @@
 |:--|:--|:--|:--|:--|:--|
 |go|[0]|rw|0x0||Sets the start for the DMA operation|
 |abort|[1]|rw|0x0||Stop DMA operation|
+|max_burst|[9:2]|rw|0xff||Max burst length (ALEN) in the AXI txn|
 
 ### <div id="csr_dma-dma_status"></div>dma_status
 

csr_out/csr_dma.sv

@@ -23,6 +23,7 @@ module csr_dma
   rggen_axi4lite_if.slave axi4lite_if,
   output logic o_dma_control_go,
   output logic o_dma_control_abort,
+  output logic [7:0] o_dma_control_max_burst,
   input logic i_dma_status_done,
   input logic [31:0] i_dma_error_error_addr,
   input logic i_dma_error_error_type,
@@ -63,7 +64,7 @@ module csr_dma
       .OFFSET_ADDRESS (8'h00),
       .BUS_WIDTH      (64),
       .DATA_WIDTH     (64),
-      .VALID_BITS     (64'h0000000000000003),
+      .VALID_BITS     (64'h00000000000003ff),
       .REGISTER_INDEX (0)
     ) u_register (
       .i_clk        (i_clk),
@@ -123,6 +124,32 @@ module csr_dma
         .o_value_unmasked   ()
       );
     end
+    if (1) begin : g_max_burst
+      localparam bit [7:0] INITIAL_VALUE = 8'hff;
+      rggen_bit_field_if #(8) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 8)
+      rggen_bit_field #(
+        .WIDTH          (8),
+        .INITIAL_VALUE  (INITIAL_VALUE),
+        .SW_WRITE_ONCE  (0),
+        .TRIGGER        (0)
+      ) u_bit_field (
+        .i_clk              (i_clk),
+        .i_rst_n            (i_rst_n),
+        .bit_field_if       (bit_field_sub_if),
+        .o_write_trigger    (),
+        .o_read_trigger     (),
+        .i_sw_write_enable  ('1),
+        .i_hw_write_enable  ('0),
+        .i_hw_write_data    ('0),
+        .i_hw_set           ('0),
+        .i_hw_clear         ('0),
+        .i_value            ('0),
+        .i_mask             ('1),
+        .o_value            (o_dma_control_max_burst),
+        .o_value_unmasked   ()
+      );
+    end
   end endgenerate
   generate if (1) begin : g_dma_status
     rggen_bit_field_if #(64) bit_field_if();

csr_out/csr_dma.v

@@ -35,6 +35,7 @@ module csr_dma #(
   output [1:0] o_rresp,
   output o_dma_control_go,
   output o_dma_control_abort,
+  output [7:0] o_dma_control_max_burst,
   input i_dma_status_done,
   input [31:0] i_dma_error_error_addr,
   input i_dma_error_error_type,
@@ -112,7 +113,7 @@ module csr_dma #(
     wire [63:0] w_bit_field_write_data;
     wire [63:0] w_bit_field_read_data;
     wire [63:0] w_bit_field_value;
-    `rggen_tie_off_unused_signals(64, 64'h0000000000000003, w_bit_field_read_data, w_bit_field_value)
+    `rggen_tie_off_unused_signals(64, 64'h00000000000003ff, w_bit_field_read_data, w_bit_field_value)
     rggen_default_register #(
       .READABLE       (1),
       .WRITABLE       (1),
@@ -197,6 +198,34 @@ module csr_dma #(
         .o_value_unmasked   ()
       );
     end
+    if (1) begin : g_max_burst
+      rggen_bit_field #(
+        .WIDTH          (8),
+        .INITIAL_VALUE  (`rggen_slice(8'hff, 8, 0)),
+        .SW_WRITE_ONCE  (0),
+        .TRIGGER        (0)
+      ) u_bit_field (
+        .i_clk              (i_clk),
+        .i_rst_n            (i_rst_n),
+        .i_sw_valid         (w_bit_field_valid),
+        .i_sw_read_mask     (w_bit_field_read_mask[2+:8]),
+        .i_sw_write_enable  (1'b1),
+        .i_sw_write_mask    (w_bit_field_write_mask[2+:8]),
+        .i_sw_write_data    (w_bit_field_write_data[2+:8]),
+        .o_sw_read_data     (w_bit_field_read_data[2+:8]),
+        .o_sw_value         (w_bit_field_value[2+:8]),
+        .o_write_trigger    (),
+        .o_read_trigger     (),
+        .i_hw_write_enable  (1'b0),
+        .i_hw_write_data    ({8{1'b0}}),
+        .i_hw_set           ({8{1'b0}}),
+        .i_hw_clear         ({8{1'b0}}),
+        .i_value            ({8{1'b0}}),
+        .i_mask             ({8{1'b1}}),
+        .o_value            (o_dma_control_max_burst),
+        .o_value_unmasked   ()
+      );
+    end
   end endgenerate
   generate if (1) begin : g_dma_status
     wire w_bit_field_valid;

csr_out/csr_dma_ral_pkg.sv

@@ -6,12 +6,14 @@ package csr_dma_ral_pkg;
   class dma_control_reg_model extends rggen_ral_reg;
     rand rggen_ral_field go;
     rand rggen_ral_field abort;
+    rand rggen_ral_field max_burst;
     function new(string name);
       super.new(name, 64, 0);
     endfunction
     function void build();
       `rggen_ral_create_field(go, 0, 1, "RW", 0, 1'h0, 1, -1, "")
       `rggen_ral_create_field(abort, 1, 1, "RW", 0, 1'h0, 1, -1, "")
+      `rggen_ral_create_field(max_burst, 2, 8, "RW", 0, 8'hff, 1, -1, "")
     endfunction
   endclass
   class dma_status_reg_model extends rggen_ral_reg;

rtl/axi_dma_wrapper.sv

@@ -3,10 +3,10 @@
  * License           : MIT license <Check LICENSE>
  * Author            : Anderson Ignacio da Silva (aignacio) <[email protected]>
  * Date              : 06.06.2022
- * Last Modified Date: 10.06.2022
+ * Last Modified Date: 12.06.2022
  */
 module axi_dma_wrapper
-  import utils_pkg::*;
+  import dma_utils_pkg::*;
 (
   input                 clk,
   input                 rst,
@@ -30,8 +30,8 @@ module axi_dma_wrapper
   logic [`DMA_NUM_DESC-1:0]                     dma_desc_en;
 
   s_dma_desc_t  [`DMA_NUM_DESC-1:0]             dma_desc;
-  s_dma_cmd_in_t                                dma_cmd_in;
-  s_dma_cmd_in_t                                dma_cmd_out;
+  s_dma_control_t                               dma_ctrl;
+  s_dma_status_t                                dma_stats;
   s_dma_error_t                                 dma_error;
 
   always_comb begin
@@ -81,20 +81,29 @@ module axi_dma_wrapper
     .o_rid                      (),
     .o_rdata                    (dma_csr_miso_o.rdata),
     .o_rresp                    (dma_csr_miso_o.rresp),
-    .o_dma_control_go           (dma_cmd_in.go),
-    .o_dma_control_abort        (dma_cmd_in.abort),
-    .i_dma_status_done          (dma_cmd_out.done),
+    .o_dma_control_go           (dma_ctrl.go),
+    .o_dma_control_max_burst    (dma_ctrl.max_burst),
+    .o_dma_control_abort        (dma_ctrl.abort_req),
+    .i_dma_status_done          (dma_stats.done),
+    .i_dma_error_error_trig     (dma_stats.error),
     .i_dma_error_error_addr     (dma_error.addr),
     .i_dma_error_error_type     (dma_error.type_err),
     .i_dma_error_error_src      (dma_error.src),
-    .i_dma_error_error_trig     (dma_cmd_out.error),
     .o_dma_descriptor_src_addr  (dma_desc_src_vec),
     .o_dma_descriptor_dest_addr (dma_desc_dst_vec),
-    .o_dma_descriptor_num_bytes (dma_desc_num_bytes_vec),
+    .o_dma_descriptor_num_bytes (dma_desc_byt_vec),
     .o_dma_descriptor_write_mode(dma_desc_wr_mod),
     .o_dma_descriptor_read_mode (dma_desc_rd_mod),
     .o_dma_descriptor_enable    (dma_desc_en)
   );
   /* verilator lint_on WIDTH */
 
+  dma_func_wrapper u_dma_func_wrapper(
+    .clk        (clk),
+    .rst        (rst),
+    // From/To CSRs
+    .dma_ctrl_i (dma_ctrl),
+    .dma_desc_i (dma_desc),
+    .dma_stats_o(dma_stats)
+  );
 endmodule

rtl/dma_fifo.sv

@@ -0,0 +1,90 @@
+/**
+ * File              : dma_fifo.sv
+ * License           : MIT license <Check LICENSE>
+ * Author            : Anderson Ignacio da Silva (aignacio) <[email protected]>
+ * Date              : 10.06.2022
+ * Last Modified Date: 12.06.2022
+ */
+module dma_fifo
+  import dma_utils_pkg::*;
+#(
+  parameter int SLOTS = `DMA_FIFO_DEPTH,
+  parameter int WIDTH = `AXI_DATA_WIDTH
+)(
+  input                                       clk,
+  input                                       rst,
+  input                                       write_i,
+  input                                       read_i,
+  input         [WIDTH-1:0]                   data_i,
+  output  logic [WIDTH-1:0]                   data_o,
+  output  logic                               error_o,
+  output  logic                               full_o,
+  output  logic                               empty_o,
+  output  logic [$clog2(SLOTS>1?SLOTS:2):0]   ocup_o,
+  output  logic [$clog2(SLOTS>1?SLOTS:2):0]   free_o
+);
+  `define MSB_SLOT  $clog2(SLOTS>1?SLOTS:2)
+
+  logic [SLOTS-1:0] [WIDTH-1:0]     fifo_ff;
+  logic [`MSB_SLOT:0] write_ptr_ff;
+  logic [`MSB_SLOT:0] read_ptr_ff;
+  logic [`MSB_SLOT:0] next_write_ptr;
+  logic [`MSB_SLOT:0] next_read_ptr;
+  logic [`MSB_SLOT:0] fifo_ocup;
+
+  always_comb begin
+    next_read_ptr = read_ptr_ff;
+    next_write_ptr = write_ptr_ff;
+    if (SLOTS == 1) begin
+      empty_o = (write_ptr_ff == read_ptr_ff);
+      full_o  = (write_ptr_ff[0] != read_ptr_ff[0]);
+      data_o  = empty_o ? '0 : fifo_ff[0];
+    end
+    else begin
+      empty_o = (write_ptr_ff == read_ptr_ff);
+      full_o  = (write_ptr_ff[`MSB_SLOT-1:0] == read_ptr_ff[`MSB_SLOT-1:0]) &&
+                (write_ptr_ff[`MSB_SLOT] != read_ptr_ff[`MSB_SLOT]);
+      data_o  = empty_o ? '0 : fifo_ff[read_ptr_ff[`MSB_SLOT-1:0]];
+    end
+
+    if (write_i && ~full_o)
+      next_write_ptr = write_ptr_ff + 'd1;
+
+    if (read_i && ~empty_o)
+      next_read_ptr = read_ptr_ff + 'd1;
+
+    error_o = (write_i && full_o) || (read_i && empty_o);
+    fifo_ocup = write_ptr_ff - read_ptr_ff;
+    fifo_space = SLOTS - fifo_ocup;
+    ocup_o = fifo_ocup;
+  end
+
+  always_ff @ (posedge clk) begin
+    if (rst) begin
+      write_ptr_ff <= '0;
+      read_ptr_ff  <= '0;
+    end
+    else begin
+      write_ptr_ff <= next_write_ptr;
+      read_ptr_ff <= next_read_ptr;
+      if (write_i && ~full_o)
+        if (SLOTS == 1) begin
+          fifo_ff[0] <= data_i;
+        end
+        else begin
+          fifo_ff[write_ptr_ff[`MSB_SLOT-1:0]] <= data_i;
+        end
+    end
+  end
+
+`ifndef NO_ASSERTIONS
+  initial begin
+    illegal_fifo_slot : assert (2**$clog2(SLOTS) == SLOTS)
+    else $error("FIFO Slots must be power of 2");
+
+    min_fifo_size : assert (SLOTS >= 1)
+    else $error("FIFO size of SLOTS defined is illegal!");
+  end
+`endif
+
+endmodule