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Start connecting CSR I/F
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Signed-off-by: Anderson Ignacio <[email protected]>
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@aignacio
aignacio committed Jun 10, 2022
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129 changes: 129 additions & 0 deletions fmt_64.gtkw
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[*]
[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
[*] Thu Jun 9 19:32:41 2022
[*]
[dumpfile] "/Users/aignacio/projects/axi_dma/run_dir/run_verilator_test_dma_csrs_64/dump.fst"
[dumpfile_mtime] "Thu Jun 9 16:42:12 2022"
[dumpfile_size] 44974
[savefile] "/Users/aignacio/projects/axi_dma/fmt_64.gtkw"
[timestart] 0
[size] 2316 1373
[pos] 750 759
*-16.063692 84900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] .
[treeopen] .tb_axi_dma.
[treeopen] .tb_axi_dma.u_axi_dma.
[sst_width] 310
[signals_width] 332
[sst_expanded] 1
[sst_vpaned_height] 784
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tb_axi_dma.clk
tb_axi_dma.rst
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-csr_axi_if
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[color] 2
tb_axi_dma.u_axi_dma.dma_csr_mosi_i.awvalid
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tb_axi_dma.u_axi_dma.dma_csr_miso_o.awready
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tb_axi_dma.u_axi_dma.dma_csr_mosi_i.awaddr[31:0]
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tb_axi_dma.dma_s_mosi.wdata[63:0]
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tb_axi_dma.u_axi_dma.dma_csr_mosi_i.wvalid
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tb_axi_dma.u_axi_dma.dma_csr_miso_o.wready
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tb_axi_dma.u_axi_dma.dma_csr_miso_o.bresp[1:0]
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tb_axi_dma.u_axi_dma.dma_csr_miso_o.bvalid
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tb_axi_dma.u_axi_dma.dma_csr_mosi_i.bready
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@1401200
-group_end
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tb_axi_dma.u_axi_dma.dma_csr_miso_o.rvalid
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tb_axi_dma.u_axi_dma.dma_csr_miso_o.rresp[1:0]
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-csr_axi_if
[pattern_trace] 1
[pattern_trace] 0
52 changes: 37 additions & 15 deletions rtl/axi_dma_wrapper.sv
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Expand Up @@ -3,7 +3,7 @@
* License : MIT license <Check LICENSE>
* Author : Anderson Ignacio da Silva (aignacio) <[email protected]>
* Date : 06.06.2022
* Last Modified Date: 07.06.2022
* Last Modified Date: 10.06.2022
*/
module axi_dma_wrapper
import utils_pkg::*;
Expand All @@ -22,6 +22,18 @@ module axi_dma_wrapper
);
localparam AXI_DATA_WIDTH = `AXI_DATA_WIDTH;

logic [`DMA_NUM_DESC*$bits(desc_addr_t)-1:0] dma_desc_src_vec;
logic [`DMA_NUM_DESC*$bits(desc_addr_t)-1:0] dma_desc_dst_vec;
logic [`DMA_NUM_DESC*$bits(desc_num_t)-1:0] dma_desc_byt_vec;
logic [`DMA_NUM_DESC-1:0] dma_desc_wr_mod;
logic [`DMA_NUM_DESC-1:0] dma_desc_rd_mod;
logic [`DMA_NUM_DESC-1:0] dma_desc_en;

s_dma_desc_t [`DMA_NUM_DESC-1:0] dma_desc;
s_dma_cmd_in_t dma_cmd_in;
s_dma_cmd_in_t dma_cmd_out;
s_dma_error_t dma_error;

always_comb begin
dma_m_mosi_o = s_axi_mosi_t'('0);
dma_done_o = 1'b0;
Expand All @@ -30,6 +42,16 @@ module axi_dma_wrapper
if (AXI_DATA_WIDTH == 64) begin
dma_csr_miso_o.rdata[AXI_DATA_WIDTH-1:(AXI_DATA_WIDTH/2)] = '0;
end

// Hook-up Desc. CSR and DMA logic
for (int i=0; i<`DMA_NUM_DESC; i++) begin
dma_desc[i].src_addr = dma_desc_src_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];
dma_desc[i].dst_addr = dma_desc_dst_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];
dma_desc[i].num_bytes = dma_desc_byt_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];
dma_desc[i].wr_mode = dma_desc_wr_mod[i];
dma_desc[i].rd_mode = dma_desc_rd_mod[i];
dma_desc[i].enable = dma_desc_en[i];
end
end

/* verilator lint_off WIDTH */
Expand All @@ -51,27 +73,27 @@ module axi_dma_wrapper
.o_bresp (dma_csr_miso_o.bresp),
.i_arvalid (dma_csr_mosi_i.arvalid),
.o_arready (dma_csr_miso_o.arready),
.i_arid (),
.i_arid ('0),
.i_araddr (dma_csr_mosi_i.araddr),
.i_arprot (dma_csr_mosi_i.arprot),
.o_rvalid (dma_csr_miso_o.rvalid),
.i_rready (dma_csr_mosi_i.rready),
.o_rid (),
.o_rdata (dma_csr_miso_o.rdata),
.o_rresp (dma_csr_miso_o.rresp),
.o_dma_control_go (),
.o_dma_control_abort (),
.i_dma_status_done ('0),
.i_dma_error_error_addr ('0),
.i_dma_error_error_type ('0),
.i_dma_error_error_src ('0),
.i_dma_error_error_trig ('0),
.o_dma_descriptor_src_addr (),
.o_dma_descriptor_dest_addr (),
.o_dma_descriptor_num_bytes (),
.o_dma_descriptor_write_mode(),
.o_dma_descriptor_read_mode (),
.o_dma_descriptor_enable ()
.o_dma_control_go (dma_cmd_in.go),
.o_dma_control_abort (dma_cmd_in.abort),
.i_dma_status_done (dma_cmd_out.done),
.i_dma_error_error_addr (dma_error.addr),
.i_dma_error_error_type (dma_error.type_err),
.i_dma_error_error_src (dma_error.src),
.i_dma_error_error_trig (dma_cmd_out.error),
.o_dma_descriptor_src_addr (dma_desc_src_vec),
.o_dma_descriptor_dest_addr (dma_desc_dst_vec),
.o_dma_descriptor_num_bytes (dma_desc_num_bytes_vec),
.o_dma_descriptor_write_mode(dma_desc_wr_mod),
.o_dma_descriptor_read_mode (dma_desc_rd_mod),
.o_dma_descriptor_enable (dma_desc_en)
);
/* verilator lint_on WIDTH */

Expand Down
53 changes: 53 additions & 0 deletions rtl/inc/dma_pkg.svh
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`ifndef _DMA_PKG_
`define _DMA_PKG_

`ifndef DMA_NUM_DESC
`define DMA_NUM_DESC 5
`endif

`ifndef DMA_ADDR_WIDTH
`define DMA_ADDR_WIDTH 32
`endif

`ifndef DMA_BYTES_WIDTH
`define DMA_BYTES_WIDTH 32
`endif

typedef logic [`DMA_ADDR_WIDTH-1:0] desc_addr_t;
typedef logic [`DMA_BYTES_WIDTH-1:0] desc_num_t;

typedef enum logic {
DMA_ERR_CFG,
DMA_ERR_OPE
} err_type_t;

typedef enum logic {
DMA_ERR_RD,
DMA_ERR_WR
} err_src_t;

typedef struct packed {
desc_addr_t src_addr;
desc_addr_t dst_addr;
desc_num_t num_bytes;
logic wr_mode;
logic rd_mode;
logic enable;
} s_dma_desc_t;

typedef struct packed {
desc_addr_t addr;
err_type_t type_err;
err_src_t src;
} s_dma_error_t;

typedef struct packed {
logic go;
logic abort;
} s_dma_cmd_in_t;

typedef struct packed {
logic error;
logic done;
} s_dma_cmd_out_t;
`endif
1 change: 1 addition & 0 deletions rtl/inc/utils_pkg.svh
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Expand Up @@ -3,5 +3,6 @@
package utils_pkg;
//export *::*;
`include "axi_pkg.svh"
`include "dma_pkg.svh"
endpackage
`endif
4 changes: 2 additions & 2 deletions tb/test_dma_csrs.py
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Expand Up @@ -4,7 +4,7 @@
# License : MIT license <Check LICENSE>
# Author : Anderson Ignacio da Silva (aignacio) <[email protected]>
# Date : 03.06.2022
# Last Modified Date: 08.06.2022
# Last Modified Date: 09.06.2022
# Last Modified By : Anderson Ignacio da Silva (aignacio) <[email protected]>
import random
import cocotb
Expand Down Expand Up @@ -39,7 +39,7 @@ async def run_test(dut, config_clk="100MHz", idle_inserter=None, backpressure_in

#------------ Init test ------------#
for csr in dma_cfg.DMA_CSRs:
tb.log.info("CSR [%s]",csr)
tb.log.info("CSR [%s - Addr: %s]", csr, hex(dma_cfg.DMA_CSRs[csr][0]))
payload = bytearray(tb._get_random_string(length=4),'utf-8')
payload_sent = int.from_bytes(payload, byteorder='little', signed=False)
payload_sent = payload_sent & dma_cfg.DMA_CSRs[csr][1]
Expand Down

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