Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC

This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

1-bit per stage block

10-bit Pipeline ADC

10-bit DAC

System Testbench

-> Using VerilogA blocks:

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To analyze the output results:

• Using Cadence:
  Select the transient signal of the DAC's output, then use the "dft" & "dB20" functions in the ADE calculator to plot the output FFT spectrum.
  https://drive.google.com/open?id=1P0Qo3bQ7QQucbzPnD_u01404rpjmt8zj
  
• Using Matlab:
  Sample the transient signal of the DAC's output by using the "sample" function in the ADE calculator, then save tha samples in a CSV file, then Run the Matlab code on the CSV data.
  https://drive.google.com/file/d/1yapHM566FUtoERnFrU_xc2nd3FOF-ETe/view
  

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References:

My project on google drive:
https://drive.google.com/drive/folders/1W9ip4MpMZNf3IQsoFQkhgg6QaUya4Yp4
EE288 Lecture Notes:
https://drive.google.com/drive/folders/12Qqfw_TX1i7dvVVYXksaSdHV4gth1OD5
Videos on how to create VerilogA blocks for ADCs: https://drive.google.com/drive/folders/1GAobRzzFTkD6ywqSdDJUsO5g2C06hh_i
https://www.youtube.com/channel/UC7jwESeWKLcRbtxHwFS3A7Q/videos