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muhammadaldacher/README.md

Salam, I'm Muhammad Aldacher 👋

📫 How to reach me: Linkedin

-> [ Study Material ]
-> [ Projects ]
-> [ MSc Courses (SJSU) ]

Study Material

Here, I will try to organize a study roadmap for people interested in Analog & Mixed-Signal design, based on my experience & what I studied before:

  1. Analog Design Basics
  2. Digital Circuits Basics
  3. PLLs (Phase-Locked Loops)
  4. ADCs (Analog/Digital Converters)
  5. LDOs (Low-Dropout Regulators)
  6. RF receiver system
  7. IO/SERDES system
    ..................................................................................

Projects

Topic Project Year
ADCs & DACs
1 8-bit Asynchronous SAR ADC design 2020
2 1.5-bit Pipeline ADC with Boosted OpAmp 2018
3 Dynamic Comparator design 2018
4 Bootstrapped Switch design 2018
5 Current-steering DAC design 2018
6 Modeling of 4-bit Flash ADC & DAC 2018
7 Modeling of 10-bit Pipeline ADC & DAC 2018
Clocking
8 10-GHz Standing-Wave based Clock-Distribution Network design 2022
9 1.9-GHz PLL design 2018
LDOs
10 LDO Regulator design 2018
RF
11 1.9-GHz-Rx-frontend blocks 2018
12 2.4-GHz LNA design 2016
SERDES
13 Transceiver for 10GbaseKR standard 2013
Layout
14 8x8 SRAM array design 2017
15 8-bit Microprocessor 2013
FPGA
16 FPGA Design of a Digital/Analog Clock Display 2017
Signal Processing
17 DTFT & Convolution 2020
18 Z Transform & Tone Reduction 2020

MSc Courses (SJSU)

Course Year Semester
1 EE223 - Analog ICs Design 2016 Fall
2 EE220 - Radio Frequency Integrated Circuits Design I 2016 Fall
3 EE178 - Digital Design with FPGA 2017 Fall
4 EE224 - High Speed CMOS 2017 Fall
5 EE288 - Data Conversion for AMS ICs 2018 Spring
6 EE295 - Technical Writing 2018 Spring
7 EE230 - Radio Frequency Integrated Circuits Design II 2018 Fall
8 EE250 - Probability 2019 Fall
9 EE210 - LinearSystems 2020 Fall

Pinned Loading

  1. Analog-Design-of-Asynchronous-SAR-ADC Analog-Design-of-Asynchronous-SAR-ADC Public

    This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

    141 18

  2. Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp Public

    This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.

    28 8

  3. FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7 FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7 Public

    The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga displ…

    VHDL 17 10

  4. Layout-Design-of-an-8x8-SRAM-array Layout-Design-of-an-8x8-SRAM-array Public

    The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static N…

    MATLAB 64 8

  5. Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC Public

    This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pi…

    MATLAB 21 11

  6. RF-design-of-1.9-GHz-Rx-frontend RF-design-of-1.9-GHz-Rx-frontend Public

    This project shows the design process of the main blocks of a typical RX frontend system.

    21 3