Darjeeling updates

.github/workflows/build_test.yaml

@@ -73,10 +73,7 @@ jobs:
         uses: actions/checkout@v4
       - name: Check execution
         run: |
-          clang-format-16 -i \
-             hw/opentitan/*.c hw/opentitan/*.h include/hw/opentitan/*.h \
-             hw/riscv/ibex*.c include/hw/riscv/ibex*.h target/riscv/ibex*.c \
-             hw/riscv/ot_*.c include/hw/riscv/ot_*.h
+          scripts/opentitan/ot-format.sh --ci -i
 
   lint-clang:
     runs-on: ubuntu-latest
@@ -100,11 +97,7 @@ jobs:
       - name: Clang tidy
         # Expect many warnings/errors (accounted but not reported) from included QEMU files
         run: |
-          clang-tidy -p build-clang \
-            hw/opentitan/*.c \
-            hw/riscv/ot_*.c  \
-            hw/riscv/ibex*.c \
-            target/riscv/ibex_csr.c
+          scripts/opentitan/ot-tidy.sh --ci -p build-clang
 
   test-clang:
     runs-on: ubuntu-latest

.gitlab-ci.d/opentitan/build.yml

@@ -23,7 +23,7 @@ build-clang:
     - git clean -dffx subprojects
     - mkdir build
     - cd build
-    - ../configure --cc=clang --disable-werror $QEMU_BUILD_OPTS
+    - ../configure --cc=clang-16 --disable-werror $QEMU_BUILD_OPTS
         --target-list=riscv32-softmmu,riscv64-softmmu,x86_64-linux-user
     - ninja
     - ninja qemu-img
@@ -62,7 +62,7 @@ format:
     - qemu_ot
   stage: build
   script:
-    - scripts/opentitan/ot-format.sh -i $(tr '\n' ' ' < .gitlab-ci.d/opentitan/$CLANG_FORMAT_CONF)
+    - scripts/opentitan/ot-format.sh --ci -i
     - git status -s
     - test $(git status -s | wc -l) -eq 0
 
@@ -72,4 +72,4 @@ tidy:
   stage: build
   needs: ["build-clang"]
   script:
-    - scripts/opentitan/ot-tidy.sh -p build $(tr '\n' ' ' < .gitlab-ci.d/opentitan/$CLANG_TIDY_CONF)
+    - scripts/opentitan/ot-tidy.sh --ci -p build

.gitlab-ci.d/opentitan/ot-bmtests.yml

@@ -19,7 +19,7 @@ baremetal-eg-tests:
     - zstd -d --stdout ot-eg-bmtest.tar.zst | tar xf - -C ${BASEDIR}
     - find ${BASEDIR}
     - scripts/opentitan/pyot.py -vv -c ${BASEDIR}/data/qemu/pyot-ot-earlgrey.hjson
-         -w ot-earlgrey.csv -R -T 3 -F '!aes-kat*'
+         -w ot-earlgrey.csv -R -T 3 -F '*' -F '!aes-kat*'
   artifacts:
     public: false
     expire_in: 1 year

.gitlab-ci.d/opentitan/qemu-ot.yml

@@ -1,10 +1,8 @@
 variables:
+  BAREMETAL_REF: "240223-1"
   QEMU_BUILD_OPTS: ""
-  CLANG_FORMAT_CONF: "ot.clang_format"
-  CLANG_TIDY_CONF: "ot.clang_tidy"
 
 include:
-  - local: '/.gitlab-ci.d/opentitan/bmref.yml'
   - local: '/.gitlab-ci.d/opentitan/build.yml'
   - local: '/.gitlab-ci.d/opentitan/ot-smoke.yml'
   - local: '/.gitlab-ci.d/opentitan/ot-bmtests.yml'

docs/opentitan/darjeeling.md

@@ -50,6 +50,7 @@ Devices in this group implement subset(s) of the real HW.
 * KMAC
   * Side loading is not supported
 * Lifecycle controller
+  * [LC controller](lc_ctrl_dmi.md) can be accessed through JTAG using a DM-TL bridge
   * Escalation is not supported
 * Power Manager
   * Fast FSM is partially supported, Slow FSM is bypassed
@@ -143,6 +144,12 @@ See [`tools.md`](tools.md)
   alternative to allow the Ibex core to execute guest code is to provide a valid OTP image with one
   of the expected LifeCycle state, such as TestUnlock*, Dev, Prod or RMA.
 
+* `-global ot-ibex_wrapper-dj.lc-ignore-ids=<ids>` acts as `lc-ignore`, enabling the selection of
+  specific ibex wrapper instance based on their unique identifiers. See `ot_id` property in the
+  machine definition file for a list of valid identifiers. `<ids>` should be defined as a comma-
+  separated list of valid identifiers. It is only possible to ignore LifeCycle states with this
+  option, not to enforce them.
+
 * `-cpu lowrisc-ibex,x-zbr=false` can be used to force disable the Zbr experimental-and-deprecated
   RISC-V bitmap extension for CRC32 extension.
 

docs/opentitan/jtagmbx.md

@@ -31,6 +31,46 @@ where:
 QEMU should be started with an option such as `-jtag tcp::3335` so that the JTAG server is
 instantiated and listen for incoming connection on TCP port 3335.
 
+#### macOS
+
+If you want to avoid the boring pop-up window from macOS
+```
+Do you want the application “qemu-system-riscv32” to accept incoming network connections?
+```
+restrict the listening interfaces to the localhost with `-jtag tcp:localhost:3335` as QEMU defaults
+to listening on all interfaces, _i.e._ 0.0.0.0
+
+## Communicating with JTAG server and JTAG MailBox using Python
+
+OpenTitan implementation provides JTAG/DTM/DMI/Mailbox stack available as Python modules:
+
+* jtag/tap module is available from `scripts/jtag` directory
+* dtm/dmi and jtag mailbox modules are available from `scripts/opentitan` directory
+
+Python snippet to create a communication channel with the VM JTAG mailbox:
+
+````py
+from socket import create_connection
+from jtag.bitbang import JtagBitbangController
+from jtag.jtag import JtagEngine
+from ot.dtm import DebugTransportModule
+from ot.mailbox.jtag import JtagMbox
+
+sock = create_connection(('localhost', 3335), timeout=1.0)
+ctrl = JtagBitbangController(sock)
+eng = JtagEngine(ctrl)
+ctrl.tap_reset(True)
+dtm = DebugTransportModule(eng, 5)  # IR length depends on the actual machine
+version, abits = dtm['dtmcs'].dmi_version, dtm['dtmcs'].abits
+print(f'DTM: v{version[0]}.{version[1]}, {abits} bits')
+dtm['dtmcs'].dmireset()
+mbj = JtagMbox(dtm, 0x2200 >> 2)
+
+# See ot.mailbox.sysmbox.SysMbox for mailbox communication API
+````
+
+## Communicating with JTAG server using OpenOCD
+
 It is possible from OpenOCD running a host to connect to the embedded JTAG server using the
 `remote_bitbang` protocol, using a configuration script such as
 

docs/opentitan/lc_ctrl_dmi.md

@@ -0,0 +1,67 @@
+# Darjeeling LifeCycle Controller over DMI
+
+## Communicating with the JTAG Mailbox through a JTAG connection
+
+In QEMU, a bridge between the Debug Module Interface (DMI) and the JTAG Mailbox is implemented
+as Debug Module bridge.
+
+```
++----------------+
+| Host (OpenOCD) |
++----------------+
+      |
+      | TCP connection ("bitbang mode")
+      |
++-----|-----------------------------------------------------------------------------------+
+|     v                                                                                   |
+| +-------------+     +-----+     +----------+         +---------+         +------+       |
+| | JTAG server |---->| DMI |---->| ot_dm_tl |====D====| LC Ctrl |====P====| Hart |       |
+| +-------------+     +-----+     +----------+         +---------+         +------+       |
+|                                                                                     QEMU|
++-----------------------------------------------------------------------------------------+
+```
+
+where:
+  `P` is the private OT bus
+  `D` is the debug bus
+
+QEMU should be started with an option such as `-jtag tcp::3335` so that the JTAG server is
+instantiated and listen for incoming connection on TCP port 3335.
+
+#### macOS
+
+If you want to avoid the boring pop-up window from macOS
+```
+Do you want the application “qemu-system-riscv32” to accept incoming network connections?
+```
+restrict the listening interfaces to the localhost with `-jtag tcp:localhost:3335` as QEMU defaults
+to listening on all interfaces, _i.e._ 0.0.0.0
+
+## Communicating with JTAG server and Life Cycle controller using Python
+
+OpenTitan implementation provides JTAG/DTM/DMI/Mailbox stack available as Python modules:
+
+* jtag/tap module is available from `scripts/jtag` directory
+* dtm/dmi and jtag mailbox modules are available from `scripts/opentitan` directory
+
+Python snippet to create a communication channel with the VM JTAG mailbox:
+
+````py
+from socket import create_connection
+from jtag.bitbang import JtagBitbangController
+from jtag.jtag import JtagEngine
+from ot.dtm import DebugTransportModule
+from ot.lc_ctrl.lcdmi import LifeCycleController
+
+sock = create_connection(('localhost', 3335), timeout=1.0)
+ctrl = JtagBitbangController(sock)
+eng = JtagEngine(ctrl)
+ctrl.tap_reset(True)
+dtm = DebugTransportModule(eng, 5)  # IR length depends on the actual machine
+version, abits = dtm['dtmcs'].dmi_version, dtm['dtmcs'].abits
+print(f'DTM: v{version[0]}.{version[1]}, {abits} bits')
+dtm['dtmcs'].dmireset()
+lc_ctrl = LifeCycleController(dtm, 0x3000 >> 2)
+
+# See LifeCycleController for LC controller communication API
+````

docs/opentitan/tools.md

@@ -40,6 +40,14 @@ directory to help with these tasks.
 * `present.py` implements the Present 128-bit scrambler/descrambler used in OTP image files for
   HW digest verification.
 * `treillis/` directory contains the test application to test the [GPIO](gpio.md) device.
+* [`uartmux.py`](uartmux.md) is a tiny stream wrapper to help dealing with multiple QEMU output
+  streams, typically multiple virtual UARTs.
+
+## Python modules
+
+* Available from `scripts/jtag` and `scripts/opentitan/ot`
+* [JTAG mailbox](jtagmbx.md) provides an API to access the system side of the mailbox over JTAG/DMI
+* [LC DMI](lc_ctrl_dmi.md) provides an API to control the Life Cycle controller over JTAG/DMI
 
 ## Configuration files
 

docs/opentitan/uartmux.md

@@ -0,0 +1,58 @@
+# `uartmux.py`
+
+`uartmux.py` is a tiny stream wrapper to help dealing with multiple QEMU output streams, typically multiple virtual UARTs.
+
+## Usage
+
+````text
+usage: uartmux.py [-h] [-i IFACE] [-p PORT] [-c CHANNEL] [-v] [-d] [name ...]
+
+QEMU UART muxer.
+
+positional arguments:
+  name                  assign name to input connection
+
+options:
+  -h, --help            show this help message and exit
+  -i IFACE, --iface IFACE
+                        specify TCP interface to listen to (default: localhost)
+  -p PORT, --port PORT  specify TCP port to listen to (default: 9000)
+  -c CHANNEL, --channel CHANNEL
+                        expected comm channel count(default: 3)
+  -s SEPARATOR, --separator SEPARATOR
+                        repeat separator between each session
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+`uartmux.py` may be used with QEMU character devices, _i.e._ `chardev` defined as network streams,
+such as `-chardev socket`.
+
+`uartmux.py` listens on multiple input streams, and prints them one line at a time, colorizing each
+stream with a different color when an ANSI terminal is used.
+
+It enables a coherent output log when multiple virtual UARTs are emitting at once.
+
+### Arguments
+
+* `name` optional name(s) for prexifing each log message line with the known channel name
+* `-c` / `--channel` how many input streams are expected, in order to assign the same ANSI color
+  to the same input stream across subsequence QEMU sessions. Note that if not defined, default to
+  the count of defined names
+* `-d` / `--debug` only useful to debug the script, reports any Python traceback to the standard
+  error stream.
+* `-i` / `--iface` select an alternative interface for listening on, default to localhost
+* `-p` / `--port` select an altenative TCP port for listening on, default to 9000
+* `-s` / `--separator` emit this separator between each detected QEMU session
+* `-v` / `--verbose` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+### Example
+
+QEMU using two virtual UART output identified as `uart0` and `uart1`:
+
+* run `uartmux.py uart0 uart1` in one terminal
+* run QEMU in another terminal with the following option switches:
+  ```
+  -chardev socket,id=uart0,host=127.0.0.1,port=9000
+  -chardev socket,id=uart1,host=127.0.0.1,port=9000
+  ```

hw/opentitan/ot_aes.c

@@ -905,7 +905,7 @@ static void ot_aes_process_cond(OtAESState *s)
                  * AES throughput.
                  */
                 timer_del(s->retard_timer);
-                uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+                uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
                 timer_mod(s->retard_timer,
                           (int64_t)(now + OT_AES_RETARD_DELAY_NS));
             } else {
@@ -1278,8 +1278,7 @@ static void ot_aes_init(Object *obj)
     ibex_qdev_init_irq(obj, &s->clkmgr, OT_CLOCK_ACTIVE);
 
     s->process_bh = qemu_bh_new(&ot_aes_handle_process, s);
-    s->retard_timer =
-        timer_new_ns(QEMU_CLOCK_VIRTUAL, &ot_aes_handle_process, s);
+    s->retard_timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_aes_handle_process, s);
 }
 
 static void ot_aes_class_init(ObjectClass *klass, void *data)

hw/opentitan/ot_aon_timer.c

@@ -34,6 +34,7 @@
 #include "qemu/timer.h"
 #include "hw/opentitan/ot_alert.h"
 #include "hw/opentitan/ot_aon_timer.h"
+#include "hw/opentitan/ot_common.h"
 #include "hw/qdev-properties.h"
 #include "hw/registerfields.h"
 #include "hw/riscv/ibex_common.h"
@@ -200,7 +201,7 @@ static void ot_aon_timer_update_irqs(OtAonTimerState *s)
 
 static void ot_aon_timer_rearm_wkup(OtAonTimerState *s, bool reset_origin)
 {
-    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
+    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
 
     if (reset_origin) {
         s->wkup_origin_ns = now;
@@ -239,7 +240,7 @@ static void ot_aon_timer_wkup_cb(void *opaque)
 
 static void ot_aon_timer_rearm_wdog(OtAonTimerState *s, bool reset_origin)
 {
-    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
+    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
 
     if (reset_origin) {
         s->wdog_origin_ns = now;
@@ -306,14 +307,14 @@ static uint64_t ot_aon_timer_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_WKUP_COUNT: {
         uint64_t now = ot_aon_timer_is_wkup_enabled(s) ?
-                           qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT) :
+                           qemu_clock_get_ns(OT_VIRTUAL_CLOCK) :
                            s->wkup_origin_ns;
         val32 = ot_aon_timer_get_wkup_count(s, now);
         break;
     }
     case R_WDOG_COUNT: {
         uint64_t now = ot_aon_timer_is_wdog_enabled(s) ?
-                           qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT) :
+                           qemu_clock_get_ns(OT_VIRTUAL_CLOCK) :
                            s->wdog_origin_ns;
         val32 = ot_aon_timer_get_wdog_count(s, now);
         break;
@@ -368,7 +369,7 @@ static void ot_aon_timer_write(void *opaque, hwaddr addr, uint64_t value,
                 /* stop timer */
                 timer_del(s->wkup_timer);
                 /* save current count */
-                uint32_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
+                uint32_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
                 s->regs[R_WKUP_COUNT] = ot_aon_timer_get_wkup_count(s, now);
                 s->wkup_origin_ns = now;
             }
@@ -401,7 +402,7 @@ static void ot_aon_timer_write(void *opaque, hwaddr addr, uint64_t value,
                     /* stop timer */
                     timer_del(s->wdog_timer);
                     /* save current count */
-                    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
+                    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
                     s->regs[R_WDOG_COUNT] = ot_aon_timer_get_wdog_count(s, now);
                     s->wdog_origin_ns = now;
                 }
@@ -435,7 +436,7 @@ static void ot_aon_timer_write(void *opaque, hwaddr addr, uint64_t value,
          * schedule the timer for the next peripheral clock tick to check again
          * for interrupt condition
          */
-        int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
+        int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
         int64_t next = ot_aon_timer_compute_next_timeout(s, now, 0);
         if (change & INTR_WKUP_TIMER_EXPIRED_MASK) {
             timer_mod_anticipate(s->wkup_timer, next);
@@ -503,10 +504,8 @@ static void ot_aon_timer_init(Object *obj)
                           TYPE_OT_AON_TIMER, REGS_SIZE);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 
-    s->wkup_timer =
-        timer_new_ns(QEMU_CLOCK_VIRTUAL_RT, &ot_aon_timer_wkup_cb, s);
-    s->wdog_timer =
-        timer_new_ns(QEMU_CLOCK_VIRTUAL_RT, &ot_aon_timer_wdog_cb, s);
+    s->wkup_timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_aon_timer_wkup_cb, s);
+    s->wdog_timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_aon_timer_wdog_cb, s);
 }
 
 static void ot_aon_timer_class_init(ObjectClass *klass, void *data)