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[pwm,dv] Exclude an unreachable item of block coverage #25135

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[pwm,dv] Exclude an unreachable item of block coverage #25135

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15 changes: 15 additions & 0 deletions hw/ip/pwm/dv/cov/manual_excl.vRefine
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Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<refinement-file-root>
<rules>
<!--
Waive block coverage for a conditional which is true if the 'we' signal is true for the
REGWEN in register in prim_subreg_arb. If the signal is true, this denotes a write to the
register from hardware but the instantiation in pwm_reg_top wires it to zero.
Comment on lines +5 to +7
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Sorry Rupert, I don't understand this: in pwm_reg_top.sv the we input of u_regwen is connected to regwen_we, and from this comment I thought that is what you refer to. Could you clarify?

-->
<rule ccType="inst"
entityName="pwm/u_reg/u_regwen/wr_en_data_arb/gen_w0c/gen_non_mubi/2"
entityType="block"
line="135"
name="exclude"></rule>
</rules>
</refinement-file-root>
5 changes: 4 additions & 1 deletion hw/ip/pwm/dv/pwm_sim_cfg.hjson
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Expand Up @@ -38,7 +38,10 @@
sim_tops: ["pwm_bind", "pwm_cov_bind", "sec_cm_prim_onehot_check_bind"]

// Coverage exclusion
xcelium_cov_refine_files: ["{proj_root}/hw/ip/pwm/dv/cov/pwm_unr_excl.vRefine"]
xcelium_cov_refine_files: [
"{proj_root}/hw/ip/pwm/dv/cov/pwm_unr_excl.vRefine"
"{proj_root}/hw/ip/pwm/dv/cov/manual_excl.vRefine"
]

// Default iterations for all tests - each test entry can override this.
reseed: 50
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