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[pwm,dv] Exclude an unreachable item of block coverage #25135

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@rswarbrick rswarbrick commented Nov 14, 2024

This cannot happen because of a constant wiring value.

Note: This PR depends on #25088. Once that is merged, this PR will only contain the last commit. (No longer true)

@rswarbrick rswarbrick added Component:DV DV issue: testbench, test case, etc. IP:pwm labels Nov 14, 2024
@rswarbrick rswarbrick requested a review from a team as a code owner November 14, 2024 11:40
@rswarbrick rswarbrick requested review from matutem and removed request for a team November 14, 2024 11:40
This cannot happen because of a constant wiring value.

Signed-off-by: Rupert Swarbrick <[email protected]>
@rswarbrick rswarbrick force-pushed the pwm-manual-exclusion-2 branch from de96e7c to 0ebaf51 Compare December 2, 2024 17:23
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I think the rejigged version of #25140 is a bit cleaner than the old version. It also no longer conflicts with this change! So I've squashed things together and the PR is now a clean single commit.

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matutem commented Dec 13, 2024

This is specific to xcelium. It is troubling since our sign-off tool is VCS. Perhaps this hole doesn't show up in VCS so an exclusion is not needed there?

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The signoff tool is defined by the block's sim_cfg hjson file. For pwm, it's xcelium.

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matutem commented Dec 18, 2024

When reviewing the block for this I noticed the registers spec is missing regwens. I filed #25688 for this.

Comment on lines +5 to +7
Waive block coverage for a conditional which is true if the 'we' signal is true for the
REGWEN in register in prim_subreg_arb. If the signal is true, this denotes a write to the
register from hardware but the instantiation in pwm_reg_top wires it to zero.
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Sorry Rupert, I don't understand this: in pwm_reg_top.sv the we input of u_regwen is connected to regwen_we, and from this comment I thought that is what you refer to. Could you clarify?

@matutem matutem self-requested a review December 18, 2024 00:12
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