[hw,dma,rtl] Remove memory limit interrupt

[Razer6]

The memory interrupt allowed the system to configure a soft and hard memory limit address. When reaching one of those limits during a DMA transfer, the DMA would fire the associated interrupt. This mode was originally designed for the hardware-handshake mode, wehere the DMA would run in a free-running approach and SW would stop the transfer manually when reaching one of those limits.

In the current design, this mode is superseded by the multi-chunk mode, where a precise number of bytes gets transferred automatically.

This PR removes that interrupt from:

• RTL
• DV
• DIF

[alees24]

Disclaimer: I haven't tried to re-run any tests and checked that this completely removes all traces of that interrupt and that everything seems work, having not worked on Darjeeling for a while.

[Razer6]

The full regression suite is passing:

### Test Results
|  Stage  |                   Name                    | Tests                          |  Max Job Runtime  |  Simulated Time  |  Passing  |  Total  |  Pass Rate  |
|:-------:|:-----------------------------------------:|:-------------------------------|:-----------------:|:----------------:|:---------:|:-------:|:-----------:|
|   V1    |             dma_memory_smoke              | dma_memory_smoke               |      37.000s      |     2.418ms      |     1     |    1    |  100.00 %   |
|   V1    |            dma_handshake_smoke            | dma_handshake_smoke            |      49.000s      |    329.149us     |     1     |    1    |  100.00 %   |
|   V1    |             dma_generic_smoke             | dma_generic_smoke              |      40.000s      |    256.916us     |     1     |    1    |  100.00 %   |
|   V1    |               csr_hw_reset                | dma_csr_hw_reset               |      11.000s      |     27.932us     |     1     |    1    |  100.00 %   |
|   V1    |                  csr_rw                   | dma_csr_rw                     |      11.000s      |     23.617us     |     1     |    1    |  100.00 %   |
|   V1    |               csr_bit_bash                | dma_csr_bit_bash               |      48.000s      |    596.096us     |     1     |    1    |  100.00 %   |
|   V1    |               csr_aliasing                | dma_csr_aliasing               |      32.000s      |     1.480ms      |     1     |    1    |  100.00 %   |
|   V1    |        csr_mem_rw_with_rand_reset         | dma_csr_mem_rw_with_rand_reset |      9.000s       |     57.573us     |     1     |    1    |  100.00 %   |
|   V1    | regwen_csr_and_corresponding_lockable_csr | dma_csr_rw                     |      11.000s      |     23.617us     |     1     |    1    |  100.00 %   |
|         |                                           | dma_csr_aliasing               |      32.000s      |     1.480ms      |     1     |    1    |  100.00 %   |
|   V1    |                                           | **TOTAL**                      |                   |                  |     8     |    8    |  100.00 %   |
|   V2    |          dma_memory_region_lock           | dma_memory_region_lock         |      5.500m       |     19.725ms     |     1     |    1    |  100.00 %   |
|   V2    |           dma_handshake_stress            | dma_handshake_stress           |      7.383m       |     9.822ms      |     1     |    1    |  100.00 %   |
|   V2    |             dma_memory_stress             | dma_memory_stress              |      21.050m      |     69.119ms     |     1     |    1    |  100.00 %   |
|   V2    |            dma_generic_stress             | dma_generic_stress             |      34.350m      |    695.605ms     |     1     |    1    |  100.00 %   |
|   V2    |     dma_handshake_mem_buffer_overflow     | dma_handshake_stress           |      7.383m       |     9.822ms      |     1     |    1    |  100.00 %   |
|   V2    |                 dma_abort                 | dma_abort                      |      1.033m       |     3.985ms      |     1     |    1    |  100.00 %   |
|   V2    |              dma_stress_all               | dma_stress_all                 |      8.950m       |     50.927ms     |     1     |    1    |  100.00 %   |
|   V2    |                 intr_test                 | dma_intr_test                  |      9.000s       |     12.987us     |     1     |    1    |  100.00 %   |
|   V2    |           tl_d_oob_addr_access            | dma_tl_errors                  |      19.000s      |    227.223us     |     1     |    1    |  100.00 %   |
|   V2    |            tl_d_illegal_access            | dma_tl_errors                  |      19.000s      |    227.223us     |     1     |    1    |  100.00 %   |
|   V2    |          tl_d_outstanding_access          | dma_csr_hw_reset               |      11.000s      |     27.932us     |     1     |    1    |  100.00 %   |
|         |                                           | dma_csr_rw                     |      11.000s      |     23.617us     |     1     |    1    |  100.00 %   |
|         |                                           | dma_csr_aliasing               |      32.000s      |     1.480ms      |     1     |    1    |  100.00 %   |
|         |                                           | dma_same_csr_outstanding       |      18.000s      |    477.740us     |     1     |    1    |  100.00 %   |
|   V2    |            tl_d_partial_access            | dma_csr_hw_reset               |      11.000s      |     27.932us     |     1     |    1    |  100.00 %   |
|         |                                           | dma_csr_rw                     |      11.000s      |     23.617us     |     1     |    1    |  100.00 %   |
|         |                                           | dma_csr_aliasing               |      32.000s      |     1.480ms      |     1     |    1    |  100.00 %   |
|         |                                           | dma_same_csr_outstanding       |      18.000s      |    477.740us     |     1     |    1    |  100.00 %   |
|   V2    |                                           | **TOTAL**                      |                   |                  |     9     |    9    |  100.00 %   |
|   V2S   |          dma_illegal_addr_range           | dma_mem_enabled                |      3.683m       |    509.718us     |     1     |    1    |  100.00 %   |
|         |                                           | dma_generic_stress             |      34.350m      |    695.605ms     |     1     |    1    |  100.00 %   |
|         |                                           | dma_handshake_stress           |      7.383m       |     9.822ms      |     1     |    1    |  100.00 %   |
|   V2S   |                tl_intg_err                | dma_tl_intg_err                |      29.000s      |     87.648us     |     1     |    1    |  100.00 %   |
|   V2S   |                                           | **TOTAL**                      |                   |                  |     2     |    2    |  100.00 %   |
|         |              Unmapped tests               | dma_short_transfer             |      6.283m       |     13.189ms     |     1     |    1    |  100.00 %   |
|         |                                           | dma_longer_transfer            |      3.700m       |     2.158ms      |     1     |    1    |  100.00 %   |
|         |                                           | **TOTAL**                      |                   |                  |    21     |   21    |  100.00 %   |

[andreaskurth]

CHANGE AUTHORIZED: hw/ip/dma/data/dma.hjson
CHANGE AUTHORIZED: hw/ip/dma/rtl/dma.sv
CHANGE AUTHORIZED: hw/ip/dma/rtl/dma_reg_pkg.sv
CHANGE AUTHORIZED: hw/ip/dma/rtl/dma_reg_top.sv
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