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[sival,alert] Enable alert_handler_lpg_sleep_mode_pings test in sival environments #22994

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[sival,alert] Enable alert_handler_lpg_sleep_mode_pings test in sival environments #22994

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6c5b3c9
[sival,alert] Enable lpg_sleep_mode_pings test in more envs
jwnrt May 7, 2024
7d055a3
[sival,alert] Add correct delay for silicon to lpg_sleep_mode_pings test
jwnrt May 7, 2024
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8 changes: 4 additions & 4 deletions sw/device/tests/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -316,17 +316,17 @@ opentitan_test(
cw310 = cw310_params(
timeout = "moderate",
),
exec_env = {
exec_env = dicts.add(
# The test requires the Ibex core to wait long enough
# before checking for the ping_timeout error.
# The wait-time for the Verilator would be around
# 4s (kClockFreqPeripheralHz = 125K).
# Thus it is not recommended to run this test on
# Verilator as this wait-time looks impractical. It should still
# be run as part of the DV nightly regression.
"//hw/top_earlgrey:fpga_cw310_test_rom": None,
"//hw/top_earlgrey:sim_dv": None,
},
dicts.omit(EARLGREY_TEST_ENVS, ["//hw/top_earlgrey:sim_verilator"]),
EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
),
deps = [
"//hw/top_earlgrey:alert_handler_regs",
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
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47 changes: 30 additions & 17 deletions sw/device/tests/alert_handler_lpg_sleep_mode_pings.c
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Original file line number Diff line number Diff line change
Expand Up @@ -80,23 +80,36 @@ static void init_peripherals(void) {
*/
void wait_enough_for_alert_ping(void) {
// wait enough
if (kDeviceType == kDeviceFpgaCw310) {
// 2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)
// 2*4*(2**16)*(400ns) = 0.2s
busy_spin_micros(1000 * 200);
} else if (kDeviceType == kDeviceSimDV) {
// NUM_ALERTS*2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)
// 2*4*(2**3)*(40ns) = 3us
busy_spin_micros(3);
} else {
// Verilator
// 2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)
// 2*4*(2**16)*(8us) = 4s
// This seems to be impractical for the current clock frequency config
// of the Verilator tests (kClockFreqPeripheralHz = 125K).
LOG_FATAL("SUPPORTED PLATFORMS: DV and FPGA");
LOG_FATAL("TO SUPPORT THE PLATFORM %d, COMPUTE THE RIGHT WAIT-TIME",
kDeviceType);
switch (kDeviceType) {
case kDeviceFpgaCw310:
case kDeviceFpgaCw340:
// 2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)
// 2*4*(2**16)*(400ns) = 0.2s
busy_spin_micros(1000 * 200);
break;
case kDeviceSilicon:
// 2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)
// 2*4*(2**16)*(42ns) = 22ms
busy_spin_micros(1000 * 22);
break;
case kDeviceSimDV:
// NUM_ALERTS*2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)
// 2*4*(2**16)*(42ns) = 22ms
busy_spin_micros(1000 * 22);
break;
case kDeviceSimVerilator:
// Verilator
// 2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)
// 2*4*(2**16)*(8us) = 4s
// This seems to be impractical for the current clock frequency config
// of the Verilator tests (kClockFreqPeripheralHz = 125K).
OT_FALLTHROUGH_INTENDED;
default:
LOG_FATAL("SUPPORTED PLATFORMS: DV and FPGA");
LOG_FATAL("TO SUPPORT THE PLATFORM %d, COMPUTE THE RIGHT WAIT-TIME",
kDeviceType);
test_status_set(kTestStatusFailed);
abort();
}
}

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