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ROM cleanups and fixes #22398

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ROM cleanups and fixes #22398

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60dee0d
[sw,device,rom] Remove extra CFI counter increment
sameo Mar 29, 2024
649fff5
[sw,device,silicon_creator] Remove AST initialization
sameo Apr 2, 2024
0a5d9ad
[hw,darjeeling,dv] Fix base address for ROM1
sameo Apr 12, 2024
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2 changes: 1 addition & 1 deletion hw/top_darjeeling/dv/tb/tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -430,7 +430,7 @@ module tb;
`else
.err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32),
`endif
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_ROM0_BASE_ADDR));
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_ROM1_BASE_ADDR));
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[Rom1], `ROM1_MEM_HIER)

`uvm_info("tb.sv", "Creating mem_bkdr_util instance for OTBN IMEM", UVM_MEDIUM)
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16 changes: 0 additions & 16 deletions sw/device/silicon_creator/rom/base_rom_start.S
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Expand Up @@ -211,29 +211,13 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
li t0, 0x00000888
csrc mie, t0

// Check if AST initialization should be skipped.
li a0, (TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR + \
OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
lw t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_OFFSET(a0)
li t1, MULTIBIT_ASM_BOOL4_TRUE
bne t0, t1, .L_entropy_enable

// Copy the AST configuration from OTP.
li a0, (TOP_DARJEELING_AST_BASE_ADDR)
li a1, (TOP_DARJEELING_AST_BASE_ADDR + AST_REGAL_REG_OFFSET + 4)
li a2, (TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR + \
OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET + \
OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_OFFSET)
call crt_section_copy

// Enable jittery clock if enabled in OTP.
li a0, (TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR + \
OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
lw t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_OFFSET(a0)
li a0, TOP_DARJEELING_CLKMGR_AON_BASE_ADDR
sw t0, CLKMGR_JITTER_ENABLE_REG_OFFSET(a0)

.L_entropy_enable:
// The following sequence enables the minimum level of entropy required to
// initialize memory scrambling, as well as the entropy distribution network.
li a0, TOP_DARJEELING_CSRNG_BASE_ADDR
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10 changes: 4 additions & 6 deletions sw/device/silicon_creator/rom/second_rom.c
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Original file line number Diff line number Diff line change
Expand Up @@ -192,11 +192,9 @@ static void rom_pre_boot_check(void) {
HARDENED_CHECK_EQ(lc_state_check, lc_state);
CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomPreBootCheck, 3);

CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomPreBootCheck, 4);

// Check the ePMP state
SHUTDOWN_IF_ERROR(epmp_state_check());
CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomPreBootCheck, 5);
CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomPreBootCheck, 4);

// Check the cpuctrl CSR.
uint32_t cpuctrl_csr;
Expand All @@ -213,10 +211,10 @@ static void rom_pre_boot_check(void) {
// Check rstmgr alert and cpu info collection configuration.
SHUTDOWN_IF_ERROR(
rstmgr_info_en_check(retention_sram_get()->creator.reset_reasons));
CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomPreBootCheck, 6);
CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomPreBootCheck, 5);

sec_mmio_check_counters(/*expected_check_count=*/2);
CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomPreBootCheck, 7);
CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomPreBootCheck, 6);
}

/**
Expand All @@ -231,7 +229,7 @@ static rom_error_t rom_try_boot(void) {
kCfiRomPreBootCheck);
rom_pre_boot_check();
CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomTryBoot, 4);
CFI_FUNC_COUNTER_CHECK(rom_counters, kCfiRomPreBootCheck, 8);
CFI_FUNC_COUNTER_CHECK(rom_counters, kCfiRomPreBootCheck, 7);

// TODO: Do not hardcode that.
uintptr_t rom_ext_lma = 0x41080000;
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