[sival,rstmgr] Adjust rstmgr_alert_info_test

Signed-off-by: Guillermo Maturana <[email protected]>

hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson

@@ -65,16 +65,14 @@
             after reset seems suitable. The `spi_host` IPs receive multiple resets so they will
             need special consideration.
 
-            SiVal: CPU must be enabled, but no other OTP or lifecycle dependencies.
+            SiVal: CPU and debug must be enabled, so it only works in TEST_UNLOCKED, DEV, and RMA.
             The rv_dm is an important tool for SiVal, so the stage is set to SV2.
             '''
       stage: V2
       si_stage: SV3
       lc_states: [
         "TEST_UNLOCKED",
         "DEV",
-        "PROD",
-        "PROD_END",
         "RMA",
       ]
       features: [
@@ -153,8 +151,7 @@
             Refer to `chip_sw_rstmgr_*sys_reset_info`.
 
             SiVal: CPU must be enabled, but no other OTP or lifecycle dependencies.
-            This can be an important diagnostic tool, so setting it to SV2.
-            This test already runs in CW310.
+            This can be an important diagnostic tool, so setting it to SV3.
             '''
       stage: V2
       si_stage: SV3
@@ -170,12 +167,7 @@
         "RSTMGR.ALERT_INFO.ENABLE",
       ]
       tests: ["chip_sw_rstmgr_alert_info"]
-      bazel: [
-# TODO(lowrisc/opentitan#20589): Enable these _sival tests when the bug is fixed
-#        "//sw/device/tests:rstmgr_alert_info_test_fpga_cw310_sival",
-#        "//sw/device/tests:rstmgr_alert_info_test_fpga_cw310_sival_rom_ext",
-        "//sw/device/tests:rstmgr_alert_info_test_fpga_cw310_test_rom",
-      ]
+      bazel: ["//sw/device/tests:rstmgr_alert_info_test"]
     }
     {
       name: chip_sw_rstmgr_sw_rst

sw/device/tests/BUILD

@@ -3566,8 +3566,9 @@ opentitan_test(
     srcs = ["rstmgr_alert_info_test.c"],
     exec_env = {
         # TODO(lowrisc/opentitan#20589): Enable _sival* tests when bug is fixed
-        # "//hw/top_earlgrey:fpga_cw310_sival": None,
-        # "//hw/top_earlgrey:fpga_cw310_sival_rom_ext": None,
+        "//hw/top_earlgrey:fpga_cw310_sival": None,         # Fails
+        "//hw/top_earlgrey:fpga_cw310_sival_rom_ext": None, # Fails
+        "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
         "//hw/top_earlgrey:fpga_cw310_test_rom": None,
         "//hw/top_earlgrey:silicon_creator": None,
         "//hw/top_earlgrey:silicon_owner_sival_rom_ext": "silicon_owner",
@@ -3585,6 +3586,7 @@ opentitan_test(
     deps = [
         "//hw/top_earlgrey:alert_handler_regs",
         "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//sw/device/lib/arch:boot_stage",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:memory",
         "//sw/device/lib/base:mmio",

sw/device/tests/rstmgr_alert_info_test.c

@@ -2,6 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "sw/device/lib/arch/boot_stage.h"
 #include "sw/device/lib/base/math.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_alert_handler.h"
@@ -189,6 +190,8 @@ typedef struct test_alert_info {
   alert_handler_testutils_info_t alert_info;
 } test_alert_info_t;
 
+// The expected info is set for rom_ext, meaning kBootStage set to
+// kBootStageOwner. It is adjusted in init_expected_info_for_non_rom_ext.
 static test_alert_info_t kExpectedInfo[kRoundTotal] = {
     [kRound1] =
         {
@@ -205,9 +208,9 @@ static test_alert_info_t kExpectedInfo[kRoundTotal] = {
             .test_name = "Multi classes(ClassB,C)",
             .alert_info =
                 {
-                    .class_accum_cnt = {0, 1, 4, 0},
-                    .class_esc_state = {kCstateIdle, kCstatePhase1,
-                                        kCstatePhase0, kCstateIdle},
+                    .class_accum_cnt = {0, 0, 4, 0},
+                    .class_esc_state = {kCstateIdle, kCstateIdle, kCstateIdle,
+                                        kCstateIdle},
                 },
         },
     [kRound3] =
@@ -683,9 +686,6 @@ static void init_expected_cause(void) {
       .alert_info.alert_cause[kTopEarlgreyAlertIdUart2FatalFault] = 1;
   kExpectedInfo[kRound2]
       .alert_info.alert_cause[kTopEarlgreyAlertIdUart3FatalFault] = 1;
-  kExpectedInfo[kRound2]
-      .alert_info.alert_cause[kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError] = 1;
-
   kExpectedInfo[kRound3]
       .alert_info.alert_cause[kTopEarlgreyAlertIdRvCoreIbexRecovSwErr] = 1;
   kExpectedInfo[kRound3]
@@ -695,6 +695,39 @@ static void init_expected_cause(void) {
   kExpectedInfo[kRound3]
       .alert_info.alert_cause[kTopEarlgreyAlertIdSpiHost0FatalFault] = 1;
 }
+
+// Modify kExpectedInfo for runs without rom_ext, so non-owner stages. The
+// difference is that without rom_ext we expect an otp alert in round 2.
+static void init_expected_info_for_non_rom_ext(void) {
+  if (kBootStage != kBootStageOwner) {
+    kExpectedInfo[kRound2].alert_info.class_accum_cnt[1] = 1;
+    kExpectedInfo[kRound2].alert_info.class_esc_state[1] = kCstatePhase1;
+    kExpectedInfo[kRound2]
+        .alert_info.alert_cause[kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError] =
+        1;
+  }
+}
+
+void flash_ctrl_has_faults(const dif_flash_ctrl_state_t *flash_ctrl) {
+  dif_flash_ctrl_faults_t faults = {.memory_properties_error = false};
+  CHECK_DIF_OK(dif_flash_ctrl_get_faults(flash_ctrl, &faults));
+#define PRINT_ON_VALUES(_struct, _field) \
+  if (_struct._field != 0) {             \
+    LOG_INFO("Flash_ctrl has " #_field); \
+  }
+
+  PRINT_ON_VALUES(faults, memory_properties_error);
+  PRINT_ON_VALUES(faults, read_error);
+  PRINT_ON_VALUES(faults, prog_window_error);
+  PRINT_ON_VALUES(faults, prog_type_error);
+  PRINT_ON_VALUES(faults, host_gnt_error);
+  PRINT_ON_VALUES(faults, register_integrity_error);
+  PRINT_ON_VALUES(faults, phy_integrity_error);
+  PRINT_ON_VALUES(faults, lifecycle_manager_error);
+  PRINT_ON_VALUES(faults, shadow_storage_error);
+#undef PRINT_ON_VALUES
+}
+
 bool test_main(void) {
   uint32_t event_idx = 0;
 
@@ -704,6 +737,7 @@ bool test_main(void) {
 
   // set expected values
   init_expected_cause();
+  init_expected_info_for_non_rom_ext();
 
   CHECK_DIF_OK(dif_rstmgr_init(
       mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr));
@@ -712,11 +746,12 @@ bool test_main(void) {
       &alert_handler));
   CHECK_DIF_OK(dif_rv_plic_init(
       mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR), &plic));
-
   CHECK_DIF_OK(dif_flash_ctrl_init_state(
       &flash_ctrl,
       mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR)));
 
+  flash_ctrl_has_faults(&flash_ctrl);
+
   peripheral_init();
 
   // Enable all interrupts used in this test.
@@ -745,13 +780,14 @@ bool test_main(void) {
     CHECK_STATUS_OK(ret_sram_testutils_counter_get(kEventCounter, &event_idx));
     CHECK_STATUS_OK(ret_sram_testutils_counter_increment(kEventCounter));
     LOG_INFO("Test round %d", event_idx);
-    // We need to initialize the info FLASH partitions storing the Creator and
-    // Owner secrets to avoid getting the flash controller into a fatal error
-    // state.
-    if (kDeviceType == kDeviceFpgaCw310 && rst_info & kDifRstmgrResetInfoPor) {
+    // If not running rom_ext we need to initialize the info FLASH partitions
+    // storing the Creator and Owner secrets to avoid getting the flash
+    // controller into a fatal error state.
+    if (kBootStage != kBootStageOwner) {
       CHECK_STATUS_OK(keymgr_testutils_flash_init(&flash_ctrl, &kCreatorSecret,
                                                   &kOwnerSecret));
     }
+    flash_ctrl_has_faults(&flash_ctrl);
 
     global_test_round = kRound1;
     prgm_alert_handler_round1();