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[rtl,pwrmgr] Fix escalation timeout persistence
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The escalation timeout needs to persist until reset. The timeout is detected by
clk_i, but the timeout is used to drive a flop clocked by clk_lc. This change
adds a synchronizer from clk_i to clk_lc, and a clk_lc flop reset by rst_lc_n.
The output of this flop is used to set the fault_status and as a reset request.

With this fix the pwrmgr_escalation_reset test passes at the block level.

Fixes #20516

Signed-off-by: Guillermo Maturana <[email protected]>
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@matutem
matutem committed Jan 19, 2024
1 parent b2e29a5 commit da087bb
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Showing 4 changed files with 46 additions and 6 deletions.
1 change: 1 addition & 0 deletions hw/ip_templates/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ class pwrmgr_escalation_timeout_vseq extends pwrmgr_base_vseq;
UVM_MEDIUM)
cfg.esc_clk_rst_vif.stop_clk();
cfg.clk_rst_vif.wait_clks(stop_cycles);
`uvm_info(`gfn, "Restarting escalation clock", UVM_MEDIUM)
cfg.esc_clk_rst_vif.start_clk();
cfg.esc_clk_rst_vif.wait_clks(4000);
end
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25 changes: 22 additions & 3 deletions hw/ip_templates/pwrmgr/rtl/pwrmgr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,7 @@ module pwrmgr
end

localparam int EscTimeOutCnt = 128;
logic esc_timeout;
logic esc_timeout, esc_timeout_lc_d, esc_timeout_lc_q;
// SEC_CM: ESC_RX.CLK.BKGN_CHK, ESC_RX.CLK.LOCAL_ESC
prim_clock_timeout #(
.TimeOutCnt(EscTimeOutCnt)
Expand All @@ -199,6 +199,25 @@ module pwrmgr
.timeout_o(esc_timeout)
);

prim_flop_2sync #(
.Width(1),
.ResetValue('0)
) u_esc_timeout_sync (
.clk_i(clk_lc),
.rst_ni(rst_lc_n),
.d_i(esc_timeout),
.q_o(esc_timeout_lc_d)
);

always_ff @(posedge clk_lc or negedge rst_lc_n) begin
if (!rst_lc_n) begin
esc_timeout_lc_q <= '0;
end else if (esc_timeout_lc_d) begin
// once latched, do not clear until reset
esc_timeout_lc_q <= 1'b1;
end
end


////////////////////////////
/// async declarations
Expand All @@ -210,7 +229,7 @@ module pwrmgr
assign peri_reqs_raw.rstreqs[NumRstReqs-1:0] = rstreqs_i;
assign peri_reqs_raw.rstreqs[ResetMainPwrIdx] = slow_rst_req;
// SEC_CM: ESC_RX.CLK.LOCAL_ESC, CTRL_FLOW.GLOBAL_ESC
assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout;
assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout_lc_q;
assign peri_reqs_raw.rstreqs[ResetNdmIdx] = ndm_req_valid;

////////////////////////////
Expand Down Expand Up @@ -328,7 +347,7 @@ module pwrmgr

assign hw2reg.fault_status.reg_intg_err.de = reg_intg_err;
assign hw2reg.fault_status.reg_intg_err.d = 1'b1;
assign hw2reg.fault_status.esc_timeout.de = esc_timeout;
assign hw2reg.fault_status.esc_timeout.de = esc_timeout_lc_q;
assign hw2reg.fault_status.esc_timeout.d = 1'b1;

// The main power domain glitch automatically causes a reset, so regsitering
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1 change: 1 addition & 0 deletions hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ class pwrmgr_escalation_timeout_vseq extends pwrmgr_base_vseq;
UVM_MEDIUM)
cfg.esc_clk_rst_vif.stop_clk();
cfg.clk_rst_vif.wait_clks(stop_cycles);
`uvm_info(`gfn, "Restarting escalation clock", UVM_MEDIUM)
cfg.esc_clk_rst_vif.start_clk();
cfg.esc_clk_rst_vif.wait_clks(4000);
end
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25 changes: 22 additions & 3 deletions hw/top_earlgrey/ip_autogen/pwrmgr/rtl/pwrmgr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,7 @@ module pwrmgr
end

localparam int EscTimeOutCnt = 128;
logic esc_timeout;
logic esc_timeout, esc_timeout_lc_d, esc_timeout_lc_q;
// SEC_CM: ESC_RX.CLK.BKGN_CHK, ESC_RX.CLK.LOCAL_ESC
prim_clock_timeout #(
.TimeOutCnt(EscTimeOutCnt)
Expand All @@ -199,6 +199,25 @@ module pwrmgr
.timeout_o(esc_timeout)
);

prim_flop_2sync #(
.Width(1),
.ResetValue('0)
) u_esc_timeout_sync (
.clk_i(clk_lc),
.rst_ni(rst_lc_n),
.d_i(esc_timeout),
.q_o(esc_timeout_lc_d)
);

always_ff @(posedge clk_lc or negedge rst_lc_n) begin
if (!rst_lc_n) begin
esc_timeout_lc_q <= '0;
end else if (esc_timeout_lc_d) begin
// once latched, do not clear until reset
esc_timeout_lc_q <= 1'b1;
end
end


////////////////////////////
/// async declarations
Expand All @@ -210,7 +229,7 @@ module pwrmgr
assign peri_reqs_raw.rstreqs[NumRstReqs-1:0] = rstreqs_i;
assign peri_reqs_raw.rstreqs[ResetMainPwrIdx] = slow_rst_req;
// SEC_CM: ESC_RX.CLK.LOCAL_ESC, CTRL_FLOW.GLOBAL_ESC
assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout;
assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout_lc_q;
assign peri_reqs_raw.rstreqs[ResetNdmIdx] = ndm_req_valid;

////////////////////////////
Expand Down Expand Up @@ -328,7 +347,7 @@ module pwrmgr

assign hw2reg.fault_status.reg_intg_err.de = reg_intg_err;
assign hw2reg.fault_status.reg_intg_err.d = 1'b1;
assign hw2reg.fault_status.esc_timeout.de = esc_timeout;
assign hw2reg.fault_status.esc_timeout.de = esc_timeout_lc_q;
assign hw2reg.fault_status.esc_timeout.d = 1'b1;

// The main power domain glitch automatically causes a reset, so regsitering
Expand Down

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