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[dv] moved tl_access_timeout_ns to CIP CFG object
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Chip Earlgrey failed to elaborate since it didn't have a reference to
'tl_access_timeout_ns' in its config object.
Added timeout variable to cip_base_env_cfg and removed it from ROM CTRL
config object

Signed-off-by: Antonio Martinez Zambrana <[email protected]>
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antmarzam committed Jan 16, 2024
1 parent fa5b861 commit 38f283f
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Showing 2 changed files with 9 additions and 5 deletions.
3 changes: 3 additions & 0 deletions hw/dv/sv/cip_lib/cip_base_env_cfg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,9 @@ class cip_base_env_cfg #(type RAL_T = dv_base_reg_block) extends dv_base_env_cfg
// Flag to indicate if it is an IP or chip level testbench.
bit is_chip;

//Default timeout of 10ms on TL accesses
uint tl_access_timeout_ns = 10_000_000; // 10ms

// Similar to the associative array above, if DUT has shadow registers, these two associative
// arrays contains register fields related to shadow register's update and storage error status.
uvm_reg_data_t shadow_update_err_status_fields[dv_base_reg_field];
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11 changes: 6 additions & 5 deletions hw/ip/rom_ctrl/dv/env/rom_ctrl_env_cfg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -16,11 +16,6 @@ class rom_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(rom_ctrl_regs_reg_block
// Enables/disable all protocol delays.
rand bit zero_delays;

// Default is 10ms (see default_spinwait_timeout_ns in csr_utils_pkg.sv)
// We have to increase this here since the ROM check may actually take longer than that,
// which sometimes causes blocked TL accesses to time out.
uint tl_access_timeout_ns = 40_000_000; // 40ms

// Bias randomization in favor of enabling zero delays less often.
constraint zero_delays_c {
zero_delays dist { 0 := 8,
Expand Down Expand Up @@ -70,6 +65,12 @@ class rom_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(rom_ctrl_regs_reg_block
// Tell the CIP base code what bit gets set if we see a TL fault.
tl_intg_alert_fields[ral.fatal_alert_cause.integrity_error] = 1;
sec_cm_alert_name = "fatal";

// Default is 10ms (see default_spinwait_timeout_ns in csr_utils_pkg.sv)
// We have to increase this here since the ROM check may actually take longer than that,
// which sometimes causes blocked TL accesses to time out.
tl_access_timeout_ns = 40_000_000; // 40ms

endfunction

endclass

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